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drm/i915/icl: Define Panel power ctrl register 

There are two panel power sequencers. Each register
has two addressable instances. This patch defines
both the instances of Panel power control register

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/99bb687b17a9165527a6210a79271c8175c8a4e3.1543500286.git.jani.nikula@intel.com
This commit is contained in:
Madhav Chauhan 2018-11-29 16:12:30 +02:00 committed by Jani Nikula
parent 05f2f03dd2
commit f4ff212030
1 changed files with 11 additions and 0 deletions
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11
drivers/gpu/drm/i915/i915_reg.h
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@ -4618,6 +4618,17 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
#define PP_ON (1 << 31)
#define _PP_CONTROL_1 0xc7204
#define _PP_CONTROL_2 0xc7304
#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
_PP_CONTROL_2)
#define POWER_CYCLE_DELAY_MASK (0x1f << 4)
#define POWER_CYCLE_DELAY_SHIFT 4
#define VDD_OVERRIDE_FORCE (1 << 3)
#define BACKLIGHT_ENABLE (1 << 2)
#define PWR_DOWN_ON_RESET (1 << 1)
#define PWR_STATE_TARGET (1 << 0)
/*
* Indicates that all dependencies of the panel are on:
*