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arm64: dts: imx8mm-beacon: Enable PCIe 

The baseboard supports a PCIe slot with a 100MHz reference clock,
but it's controlled by a different GPIO, so a gated clock is
required.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Adam Ford 2022-02-05 11:31:01 -06:00 committed by Shawn Guo
parent 6a57f224f7
commit f471b9a526
1 changed files with 57 additions and 0 deletions
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57
arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
View File

@ -3,6 +3,8 @@
* Copyright 2020 Compass Electronics Group, LLC
*/
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
leds {
compatible = "gpio-leds";
@ -34,6 +36,19 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie0_refclk_gated: pcie0-refclk-gated {
compatible = "gpio-gate-clock";
clocks = <&pcie0_refclk>;
#clock-cells = <0>;
enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
@ -64,6 +79,16 @@
startup-delay-us = <100000>;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "pci_pwr_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
@ -202,6 +227,32 @@
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk_gated>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk_gated>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
vpcie-supply = <&reg_pcie0>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@ -308,6 +359,12 @@
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6