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Merge branch 'next-exynos4' into for-next

This commit is contained in:
Kukjin Kim 2011-03-11 11:05:46 +09:00
parent a5abba989d 30d8bead5a
commit f4612798a1
78 changed files with 3064 additions and 1532 deletions
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14
arch/arm/Kconfig
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@ -760,8 +760,8 @@ config ARCH_S5PV210
help
Samsung S5PV210/S5PC110 series based systems
config ARCH_S5PV310
bool "Samsung S5PV310/S5PC210"
config ARCH_EXYNOS4
bool "Samsung EXYNOS4"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO
@ -772,7 +772,7 @@ config ARCH_S5PV310
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
help
Samsung S5PV310 series based systems
Samsung EXYNOS4 series based systems
config ARCH_SHARK
bool "Shark"
@ -991,7 +991,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
source "arch/arm/mach-s5pv210/Kconfig"
source "arch/arm/mach-s5pv310/Kconfig"
source "arch/arm/mach-exynos4/Kconfig"
source "arch/arm/mach-shmobile/Kconfig"
@ -1278,7 +1278,7 @@ config SMP
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
select USE_GENERIC_SMP_HELPERS
select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
@ -1366,7 +1366,7 @@ config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP
default y
select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
@ -1378,7 +1378,7 @@ source kernel/Kconfig.preempt
config HZ
int
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE

2
arch/arm/Makefile
View File

@ -178,7 +178,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5P6442) := s5p6442
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
machine-$(CONFIG_ARCH_S5PV210) := s5pv210
machine-$(CONFIG_ARCH_S5PV310) := s5pv310
machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
machine-$(CONFIG_ARCH_SA1100) := sa1100
machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile

70
arch/arm/configs/exynos4_defconfig Normal file
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@ -0,0 +1,70 @@
CONFIG_EXPERIMENTAL=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_EXYNOS4=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDKC210=y
CONFIG_MACH_SMDKV310=y
CONFIG_MACH_UNIVERSAL_C210=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_HOTPLUG_CPU=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_DEBUG_S3C_UART=1
CONFIG_CRC_CCITT=y

182
arch/arm/mach-exynos4/Kconfig Normal file
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@ -0,0 +1,182 @@
# arch/arm/mach-exynos4/Kconfig
#
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
# Configuration options for the EXYNOS4
if ARCH_EXYNOS4
config CPU_EXYNOS4210
bool
select S3C_PL330_DMA
help
Enable EXYNOS4210 CPU support
config EXYNOS4_MCT
bool "Kernel timer support by MCT"
help
Use MCT (Multi Core Timer) as kernel timers
config EXYNOS4_DEV_PD
bool
help
Compile in platform device definitions for Power Domain
config EXYNOS4_DEV_SYSMMU
bool
help
Common setup code for SYSTEM MMU in EXYNOS4
config EXYNOS4_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config EXYNOS4_SETUP_I2C2
bool
help
Common setup code for i2c bus 2.
config EXYNOS4_SETUP_I2C3
bool
help
Common setup code for i2c bus 3.
config EXYNOS4_SETUP_I2C4
bool
help
Common setup code for i2c bus 4.
config EXYNOS4_SETUP_I2C5
bool
help
Common setup code for i2c bus 5.
config EXYNOS4_SETUP_I2C6
bool
help
Common setup code for i2c bus 6.
config EXYNOS4_SETUP_I2C7
bool
help
Common setup code for i2c bus 7.
config EXYNOS4_SETUP_SDHCI
bool
select EXYNOS4_SETUP_SDHCI_GPIO
help
Internal helper functions for EXYNOS4 based SDHCI systems.
config EXYNOS4_SETUP_SDHCI_GPIO
bool
help
Common setup code for SDHCI gpio.
# machine support
menu "EXYNOS4 Machines"
config MACH_SMDKC210
bool "SMDKC210"
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung SMDKC210
config MACH_SMDKV310
bool "SMDKV310"
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung SMDKV310
config MACH_ARMLEX4210
bool "ARMLEX4210"
select CPU_EXYNOS4210
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select EXYNOS4_DEV_SYSMMU
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung ARMLEX4210 based on EXYNOS4210
config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board"
select CPU_EXYNOS4210
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C5
select S5P_DEV_ONENAND
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
help
Machine support for Samsung Mobile Universal S5PC210 Reference
Board.
config MACH_NURI
bool "Mobile NURI Board"
select CPU_EXYNOS4210
select S3C_DEV_WDT
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C5
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select SAMSUNG_DEV_PWM
help
Machine support for Samsung Mobile NURI Board.
endmenu
comment "Configuration for HSMMC bus width"
menu "Use 8-bit bus width"
config EXYNOS4_SDHCI_CH0_8BIT
bool "Channel 0 with 8-bit bus"
help
Support HSMMC Channel 0 8-bit bus.
If selected, Channel 1 is disabled.
config EXYNOS4_SDHCI_CH2_8BIT
bool "Channel 2 with 8-bit bus"
help
Support HSMMC Channel 2 8-bit bus.
If selected, Channel 3 is disabled.
endmenu
endif

52
arch/arm/mach-exynos4/Makefile Normal file
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@ -0,0 +1,52 @@
# arch/arm/mach-exynos4/Makefile
#
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
ifeq ($(CONFIG_EXYNOS4_MCT),y)
obj-y += mct.o
else
obj-y += time.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
endif
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
# machine support
obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
obj-$(CONFIG_MACH_NURI) += mach-nuri.o
# device support
obj-y += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o

0
arch/arm/mach-s5pv310/Makefile.boot → arch/arm/mach-exynos4/Makefile.boot
View File

191
arch/arm/mach-s5pv310/clock.c → arch/arm/mach-exynos4/clock.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/clock.c
/* linux/arch/arm/mach-exynos4/clock.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Clock support
* EXYNOS4 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -46,72 +46,72 @@ static struct clk clk_sclk_usbphy1 = {
.id = -1,
};
static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
}
static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
}
static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
}
static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
}
static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
}
static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}
static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
}
static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
}
static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
}
static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
}
static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
}
static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
}
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
}
static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
}
@ -358,7 +358,7 @@ static struct clksrc_clk clk_vpllsrc = {
.clk = {
.name = "vpll_src",
.id = -1,
.enable = s5pv310_clksrc_mask_top_ctrl,
.enable = exynos4_clksrc_mask_top_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_vpllsrc,
@ -389,205 +389,206 @@ static struct clk init_clocks_off[] = {
.name = "timers",
.id = -1,
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1<<24),
}, {
.name = "csis",
.id = 0,
.enable = s5pv310_clk_ip_cam_ctrl,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "csis",
.id = 1,
.enable = s5pv310_clk_ip_cam_ctrl,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "fimc",
.id = 0,
.enable = s5pv310_clk_ip_cam_ctrl,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimc",
.id = 1,
.enable = s5pv310_clk_ip_cam_ctrl,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
.id = 2,
.enable = s5pv310_clk_ip_cam_ctrl,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
.id = 3,
.enable = s5pv310_clk_ip_cam_ctrl,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimd",
.id = 0,
.enable = s5pv310_clk_ip_lcd0_ctrl,
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimd",
.id = 1,
.enable = s5pv310_clk_ip_lcd1_ctrl,
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "hsmmc",
.id = 0,
.parent = &clk_aclk_133.clk,
.enable = s5pv310_clk_ip_fsys_ctrl,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
.id = 1,
.parent = &clk_aclk_133.clk,
.enable = s5pv310_clk_ip_fsys_ctrl,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
.id = 2,
.parent = &clk_aclk_133.clk,
.enable = s5pv310_clk_ip_fsys_ctrl,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
.id = 3,
.parent = &clk_aclk_133.clk,
.enable = s5pv310_clk_ip_fsys_ctrl,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "hsmmc",
.id = 4,
.parent = &clk_aclk_133.clk,
.enable = s5pv310_clk_ip_fsys_ctrl,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "sata",
.id = -1,
.enable = s5pv310_clk_ip_fsys_ctrl,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "pdma",
.id = 0,
.enable = s5pv310_clk_ip_fsys_ctrl,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "pdma",
.id = 1,
.enable = s5pv310_clk_ip_fsys_ctrl,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "adc",
.id = -1,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "rtc",
.id = -1,
.enable = s5pv310_clk_ip_perir_ctrl,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "watchdog",
.id = -1,
.enable = s5pv310_clk_ip_perir_ctrl,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "usbhost",
.id = -1,
.enable = s5pv310_clk_ip_fsys_ctrl ,
.enable = exynos4_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 12),
}, {
.name = "otg",
.id = -1,
.enable = s5pv310_clk_ip_fsys_ctrl,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "spi",
.id = 0,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "iis",
.id = 0,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "iis",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "iis",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "ac97",
.id = -1,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "fimg2d",
.id = -1,
.enable = s5pv310_clk_ip_image_ctrl,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "i2c",
.id = 0,
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "i2c",
.id = 1,
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "i2c",
.id = 2,
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "i2c",
.id = 3,
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
.id = 4,
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
.id = 5,
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "i2c",
.id = 6,
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
.id = 7,
.parent = &clk_aclk_100.clk,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 13),
},
};
@ -596,32 +597,32 @@ static struct clk init_clocks[] = {
{
.name = "uart",
.id = 0,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.id = 3,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.id = 4,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
.id = 5,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
}
};
@ -746,7 +747,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 0,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_group,
@ -756,7 +757,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 1,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &clkset_group,
@ -766,7 +767,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 2,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &clkset_group,
@ -776,7 +777,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 3,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &clkset_group,
@ -786,7 +787,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_pwm",
.id = -1,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_group,
@ -796,7 +797,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_csis",
.id = 0,
.enable = s5pv310_clksrc_mask_cam_ctrl,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_group,
@ -806,7 +807,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_csis",
.id = 1,
.enable = s5pv310_clksrc_mask_cam_ctrl,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 28),
},
.sources = &clkset_group,
@ -816,7 +817,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_cam",
.id = 0,
.enable = s5pv310_clksrc_mask_cam_ctrl,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16),
},
.sources = &clkset_group,
@ -826,7 +827,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_cam",
.id = 1,
.enable = s5pv310_clksrc_mask_cam_ctrl,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20),
},
.sources = &clkset_group,
@ -836,7 +837,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_fimc",
.id = 0,
.enable = s5pv310_clksrc_mask_cam_ctrl,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_group,
@ -846,7 +847,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_fimc",
.id = 1,
.enable = s5pv310_clksrc_mask_cam_ctrl,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &clkset_group,
@ -856,7 +857,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_fimc",
.id = 2,
.enable = s5pv310_clksrc_mask_cam_ctrl,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &clkset_group,
@ -866,7 +867,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_fimc",
.id = 3,
.enable = s5pv310_clksrc_mask_cam_ctrl,
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &clkset_group,
@ -876,7 +877,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_fimd",
.id = 0,
.enable = s5pv310_clksrc_mask_lcd0_ctrl,
.enable = exynos4_clksrc_mask_lcd0_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_group,
@ -886,7 +887,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_fimd",
.id = 1,
.enable = s5pv310_clksrc_mask_lcd1_ctrl,
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_group,
@ -896,7 +897,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_sata",
.id = -1,
.enable = s5pv310_clksrc_mask_fsys_ctrl,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_mout_corebus,
@ -906,7 +907,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_spi",
.id = 0,
.enable = s5pv310_clksrc_mask_peril1_ctrl,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
.sources = &clkset_group,
@ -916,7 +917,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_spi",
.id = 1,
.enable = s5pv310_clksrc_mask_peril1_ctrl,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
.sources = &clkset_group,
@ -926,7 +927,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_spi",
.id = 2,
.enable = s5pv310_clksrc_mask_peril1_ctrl,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_group,
@ -945,7 +946,7 @@ static struct clksrc_clk clksrcs[] = {
.name = "sclk_mmc",
.id = 0,
.parent = &clk_dout_mmc0.clk,
.enable = s5pv310_clksrc_mask_fsys_ctrl,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
},
.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
@ -954,7 +955,7 @@ static struct clksrc_clk clksrcs[] = {
.name = "sclk_mmc",
.id = 1,
.parent = &clk_dout_mmc1.clk,
.enable = s5pv310_clksrc_mask_fsys_ctrl,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
},
.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
@ -963,7 +964,7 @@ static struct clksrc_clk clksrcs[] = {
.name = "sclk_mmc",
.id = 2,
.parent = &clk_dout_mmc2.clk,
.enable = s5pv310_clksrc_mask_fsys_ctrl,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
},
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
@ -972,7 +973,7 @@ static struct clksrc_clk clksrcs[] = {
.name = "sclk_mmc",
.id = 3,
.parent = &clk_dout_mmc3.clk,
.enable = s5pv310_clksrc_mask_fsys_ctrl,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
},
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
@ -981,7 +982,7 @@ static struct clksrc_clk clksrcs[] = {
.name = "sclk_mmc",
.id = 4,
.parent = &clk_dout_mmc4.clk,
.enable = s5pv310_clksrc_mask_fsys_ctrl,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16),
},
.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
@ -1022,16 +1023,16 @@ static struct clksrc_clk *sysclks[] = {
static int xtal_rate;
static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk)
static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
{
return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
}
static struct clk_ops s5pv310_fout_apll_ops = {
.get_rate = s5pv310_fout_apll_get_rate,
static struct clk_ops exynos4_fout_apll_ops = {
.get_rate = exynos4_fout_apll_get_rate,
};
void __init_or_cpufreq s5pv310_setup_clocks(void)
void __init_or_cpufreq exynos4_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long apll;
@ -1070,12 +1071,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
__raw_readl(S5P_VPLL_CON1), pll_4650);
clk_fout_apll.ops = &s5pv310_fout_apll_ops;
clk_fout_apll.ops = &exynos4_fout_apll_ops;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_vpll.rate = vpll;
printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
apll, mpll, epll, vpll);
armclk = clk_get_rate(&clk_armclk.clk);
@ -1086,7 +1087,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
aclk_160 = clk_get_rate(&clk_aclk_160.clk);
aclk_133 = clk_get_rate(&clk_aclk_133.clk);
printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
"ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
armclk, sclk_dmc, aclk_200,
aclk_100, aclk_160, aclk_133);
@ -1103,7 +1104,7 @@ static struct clk *clks[] __initdata = {
/* Nothing here yet */
};
void __init s5pv310_register_clocks(void)
void __init exynos4_register_clocks(void)
{
int ptr;

92
arch/arm/mach-s5pv310/cpu.c → arch/arm/mach-exynos4/cpu.c
View File

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5pv310/cpu.c
/* linux/arch/arm/mach-exynos4/cpu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -19,7 +19,7 @@
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/s5pv310.h>
#include <plat/exynos4.h>
#include <plat/sdhci.h>
#include <mach/regs-irq.h>
@ -29,55 +29,60 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
/* Initial IO mappings */
static struct map_desc s5pv310_iodesc[] __initdata = {
static struct map_desc exynos4_iodesc[] __initdata = {
{
.virtual = (unsigned long)S5P_VA_SYSTIMER,
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_CMU,
.pfn = __phys_to_pfn(S5PV310_PA_CMU),
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
.length = SZ_128K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_PMU,
.pfn = __phys_to_pfn(S5PV310_PA_PMU),
.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
.length = SZ_64K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
.pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_L2CC,
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO1,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO2,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO2),
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_GPIO3,
.pfn = __phys_to_pfn(S5PV310_PA_GPIO3),
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
.length = SZ_256,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_DMC0,
.pfn = __phys_to_pfn(S5PV310_PA_DMC0),
.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
@ -87,13 +92,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SROMC,
.pfn = __phys_to_pfn(S5PV310_PA_SROMC),
.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static void s5pv310_idle(void)
static void exynos4_idle(void)
{
if (!need_resched())
cpu_do_idle();
@ -101,32 +106,33 @@ static void s5pv310_idle(void)
local_irq_enable();
}
/* s5pv310_map_io
/*
* exynos4_map_io
*
* register the standard cpu IO areas
*/
void __init s5pv310_map_io(void)
*/
void __init exynos4_map_io(void)
{
iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
/* initialize device information early */
s5pv310_default_sdhci0();
s5pv310_default_sdhci1();
s5pv310_default_sdhci2();
s5pv310_default_sdhci3();
exynos4_default_sdhci0();
exynos4_default_sdhci1();
exynos4_default_sdhci2();
exynos4_default_sdhci3();
}
void __init s5pv310_init_clocks(int xtal)
void __init exynos4_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
s5pv310_register_clocks();
s5pv310_setup_clocks();
exynos4_register_clocks();
exynos4_setup_clocks();
}
void __init s5pv310_init_irq(void)
void __init exynos4_init_irq(void)
{
int irq;
@ -148,29 +154,29 @@ void __init s5pv310_init_irq(void)
}
/* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because S5PV310
* Theses parameters should be NULL and 0 because EXYNOS4
* uses GIC instead of VIC.
*/
s5p_init_irq(NULL, 0);
}
struct sysdev_class s5pv310_sysclass = {
.name = "s5pv310-core",
struct sysdev_class exynos4_sysclass = {
.name = "exynos4-core",
};
static struct sys_device s5pv310_sysdev = {
.cls = &s5pv310_sysclass,
static struct sys_device exynos4_sysdev = {
.cls = &exynos4_sysclass,
};
static int __init s5pv310_core_init(void)
static int __init exynos4_core_init(void)
{
return sysdev_class_register(&s5pv310_sysclass);
return sysdev_class_register(&exynos4_sysclass);
}
core_initcall(s5pv310_core_init);
core_initcall(exynos4_core_init);
#ifdef CONFIG_CACHE_L2X0
static int __init s5pv310_l2x0_cache_init(void)
static int __init exynos4_l2x0_cache_init(void)
{
/* TAG, Data Latency Control: 2cycle */
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
@ -188,15 +194,15 @@ static int __init s5pv310_l2x0_cache_init(void)
return 0;
}
early_initcall(s5pv310_l2x0_cache_init);
early_initcall(exynos4_l2x0_cache_init);
#endif
int __init s5pv310_init(void)
int __init exynos4_init(void)
{
printk(KERN_INFO "S5PV310: Initializing architecture\n");
printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
/* set idle function */
pm_idle = s5pv310_idle;
pm_idle = exynos4_idle;
return sysdev_register(&s5pv310_sysdev);
return sysdev_register(&exynos4_sysdev);
}

110
arch/arm/mach-s5pv310/cpufreq.c → arch/arm/mach-exynos4/cpufreq.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/cpufreq.c
/* linux/arch/arm/mach-exynos4/cpufreq.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - CPU frequency scaling support
* EXYNOS4 - CPU frequency scaling support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -31,15 +31,13 @@ static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;
#ifdef CONFIG_REGULATOR
static struct regulator *arm_regulator;
static struct regulator *int_regulator;
#endif
static struct cpufreq_freqs freqs;
static unsigned int memtype;
enum s5pv310_memory_type {
enum exynos4_memory_type {
DDR2 = 4,
LPDDR2,
DDR3,
@ -49,7 +47,7 @@ enum cpufreq_level_index {
L0, L1, L2, L3, CPUFREQ_LEVEL_END,
};
static struct cpufreq_frequency_table s5pv310_freq_table[] = {
static struct cpufreq_frequency_table exynos4_freq_table[] = {
{L0, 1000*1000},
{L1, 800*1000},
{L2, 400*1000},
@ -160,7 +158,7 @@ struct cpufreq_voltage_table {
unsigned int int_volt;
};
static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
{
.index = L0,
.arm_volt = 1200000,
@ -180,7 +178,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
},
};
static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
/* APLL FOUT L0: 1000MHz */
((250 << 16) | (6 << 8) | 1),
@ -194,17 +192,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
((200 << 16) | (6 << 8) | 4),
};
int s5pv310_verify_speed(struct cpufreq_policy *policy)
int exynos4_verify_speed(struct cpufreq_policy *policy)
{
return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
}
unsigned int s5pv310_getspeed(unsigned int cpu)
unsigned int exynos4_getspeed(unsigned int cpu)
{
return clk_get_rate(cpu_clk) / 1000;
}
void s5pv310_set_clkdiv(unsigned int div_index)
void exynos4_set_clkdiv(unsigned int div_index)
{
unsigned int tmp;
@ -321,7 +319,7 @@ void s5pv310_set_clkdiv(unsigned int div_index)
} while (tmp & 0x11);
}
static void s5pv310_set_apll(unsigned int index)
static void exynos4_set_apll(unsigned int index)
{
unsigned int tmp;
@ -340,7 +338,7 @@ static void s5pv310_set_apll(unsigned int index)
/* 3. Change PLL PMS values */
tmp = __raw_readl(S5P_APLL_CON0);
tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
tmp |= s5pv310_apll_pms_table[index];
tmp |= exynos4_apll_pms_table[index];
__raw_writel(tmp, S5P_APLL_CON0);
/* 4. wait_lock_time */
@ -357,99 +355,95 @@ static void s5pv310_set_apll(unsigned int index)
} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
}
static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
{
unsigned int tmp;
if (old_index > new_index) {
/* The frequency changing to L0 needs to change apll */
if (freqs.new == s5pv310_freq_table[L0].frequency) {
if (freqs.new == exynos4_freq_table[L0].frequency) {
/* 1. Change the system clock divider values */
s5pv310_set_clkdiv(new_index);
exynos4_set_clkdiv(new_index);
/* 2. Change the apll m,p,s value */
s5pv310_set_apll(new_index);
exynos4_set_apll(new_index);
} else {
/* 1. Change the system clock divider values */
s5pv310_set_clkdiv(new_index);
exynos4_set_clkdiv(new_index);
/* 2. Change just s value in apll m,p,s value */
tmp = __raw_readl(S5P_APLL_CON0);
tmp &= ~(0x7 << 0);
tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
__raw_writel(tmp, S5P_APLL_CON0);
}
}
else if (old_index < new_index) {
/* The frequency changing from L0 needs to change apll */
if (freqs.old == s5pv310_freq_table[L0].frequency) {
if (freqs.old == exynos4_freq_table[L0].frequency) {
/* 1. Change the apll m,p,s value */
s5pv310_set_apll(new_index);
exynos4_set_apll(new_index);
/* 2. Change the system clock divider values */
s5pv310_set_clkdiv(new_index);
exynos4_set_clkdiv(new_index);
} else {
/* 1. Change just s value in apll m,p,s value */
tmp = __raw_readl(S5P_APLL_CON0);
tmp &= ~(0x7 << 0);
tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
__raw_writel(tmp, S5P_APLL_CON0);
/* 2. Change the system clock divider values */
s5pv310_set_clkdiv(new_index);
exynos4_set_clkdiv(new_index);
}
}
}
static int s5pv310_target(struct cpufreq_policy *policy,
static int exynos4_target(struct cpufreq_policy *policy,
unsigned int target_freq,
unsigned int relation)
{
unsigned int index, old_index;
unsigned int arm_volt, int_volt;
freqs.old = s5pv310_getspeed(policy->cpu);
freqs.old = exynos4_getspeed(policy->cpu);
if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
freqs.old, relation, &old_index))
return -EINVAL;
if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
target_freq, relation, &index))
return -EINVAL;
freqs.new = s5pv310_freq_table[index].frequency;
freqs.new = exynos4_freq_table[index].frequency;
freqs.cpu = policy->cpu;
if (freqs.new == freqs.old)
return 0;
/* get the voltage value */
arm_volt = s5pv310_volt_table[index].arm_volt;
int_volt = s5pv310_volt_table[index].int_volt;
arm_volt = exynos4_volt_table[index].arm_volt;
int_volt = exynos4_volt_table[index].int_volt;
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
/* control regulator */
if (freqs.new > freqs.old) {
/* Voltage up */
#ifdef CONFIG_REGULATOR
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
regulator_set_voltage(int_regulator, int_volt, int_volt);
#endif
}
/* Clock Configuration Procedure */
s5pv310_set_frequency(old_index, index);
exynos4_set_frequency(old_index, index);
/* control regulator */
if (freqs.new < freqs.old) {
/* Voltage down */
#ifdef CONFIG_REGULATOR
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
regulator_set_voltage(int_regulator, int_volt, int_volt);
#endif
}
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
@ -458,52 +452,52 @@ static int s5pv310_target(struct cpufreq_policy *policy,
}
#ifdef CONFIG_PM
static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,
static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy,
pm_message_t pmsg)
{
return 0;
}
static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
{
return 0;
}
#endif
static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
/* set the transition latency value */
policy->cpuinfo.transition_latency = 100000;
/*
* S5PV310 multi-core processors has 2 cores
* EXYNOS4 multi-core processors has 2 cores
* that the frequency cannot be set independently.
* Each cpu is bound to the same speed.
* So the affected cpu is all of the cpus.
*/
cpumask_setall(policy->cpus);
return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
}
static struct cpufreq_driver s5pv310_driver = {
static struct cpufreq_driver exynos4_driver = {
.flags = CPUFREQ_STICKY,
.verify = s5pv310_verify_speed,
.target = s5pv310_target,
.get = s5pv310_getspeed,
.init = s5pv310_cpufreq_cpu_init,
.name = "s5pv310_cpufreq",
.verify = exynos4_verify_speed,
.target = exynos4_target,
.get = exynos4_getspeed,
.init = exynos4_cpufreq_cpu_init,
.name = "exynos4_cpufreq",
#ifdef CONFIG_PM
.suspend = s5pv310_cpufreq_suspend,
.resume = s5pv310_cpufreq_resume,
.suspend = exynos4_cpufreq_suspend,
.resume = exynos4_cpufreq_resume,
#endif
};
static int __init s5pv310_cpufreq_init(void)
static int __init exynos4_cpufreq_init(void)
{
cpu_clk = clk_get(NULL, "armclk");
if (IS_ERR(cpu_clk))
@ -521,7 +515,6 @@ static int __init s5pv310_cpufreq_init(void)
if (IS_ERR(mout_apll))
goto out;
#ifdef CONFIG_REGULATOR
arm_regulator = regulator_get(NULL, "vdd_arm");
if (IS_ERR(arm_regulator)) {
printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
@ -533,7 +526,6 @@ static int __init s5pv310_cpufreq_init(void)
printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
goto out;
}
#endif
/*
* Check DRAM type.
@ -550,7 +542,7 @@ static int __init s5pv310_cpufreq_init(void)
printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
}
return cpufreq_register_driver(&s5pv310_driver);
return cpufreq_register_driver(&exynos4_driver);
out:
if (!IS_ERR(cpu_clk))
@ -565,16 +557,14 @@ out:
if (!IS_ERR(mout_apll))
clk_put(mout_apll);
#ifdef CONFIG_REGULATOR
if (!IS_ERR(arm_regulator))
regulator_put(arm_regulator);
if (!IS_ERR(int_regulator))
regulator_put(int_regulator);
#endif
printk(KERN_ERR "%s: failed initialization\n", __func__);
return -EINVAL;
}
late_initcall(s5pv310_cpufreq_init);
late_initcall(exynos4_cpufreq_init);

143
arch/arm/mach-s5pv310/dev-audio.c → arch/arm/mach-exynos4/dev-audio.c
View File

@ -1,4 +1,7 @@
/* linux/arch/arm/mach-s5pv310/dev-audio.c
/* linux/arch/arm/mach-exynos4/dev-audio.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
@ -24,18 +27,18 @@ static const char *rclksrc[] = {
[1] = "i2sclk",
};
static int s5pv310_cfg_i2s(struct platform_device *pdev)
static int exynos4_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
break;
case 1:
s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2));
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
break;
case 2:
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4));
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
@ -46,7 +49,7 @@ static int s5pv310_cfg_i2s(struct platform_device *pdev)
}
static struct s3c_audio_pdata i2sv5_pdata = {
.cfg_gpio = s5pv310_cfg_i2s,
.cfg_gpio = exynos4_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
@ -56,10 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
},
};
static struct resource s5pv310_i2s0_resource[] = {
static struct resource exynos4_i2s0_resource[] = {
[0] = {
.start = S5PV310_PA_I2S0,
.end = S5PV310_PA_I2S0 + 0x100 - 1,
.start = EXYNOS4_PA_I2S0,
.end = EXYNOS4_PA_I2S0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -79,11 +82,11 @@ static struct resource s5pv310_i2s0_resource[] = {
},
};
struct platform_device s5pv310_device_i2s0 = {
struct platform_device exynos4_device_i2s0 = {
.name = "samsung-i2s",
.id = 0,
.num_resources = ARRAY_SIZE(s5pv310_i2s0_resource),
.resource = s5pv310_i2s0_resource,
.num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
.resource = exynos4_i2s0_resource,
.dev = {
.platform_data = &i2sv5_pdata,
},
@ -95,7 +98,7 @@ static const char *rclksrc_v3[] = {
};
static struct s3c_audio_pdata i2sv3_pdata = {
.cfg_gpio = s5pv310_cfg_i2s,
.cfg_gpio = exynos4_cfg_i2s,
.type = {
.i2s = {
.quirks = QUIRK_NO_MUXPSR,
@ -104,10 +107,10 @@ static struct s3c_audio_pdata i2sv3_pdata = {
},
};
static struct resource s5pv310_i2s1_resource[] = {
static struct resource exynos4_i2s1_resource[] = {
[0] = {
.start = S5PV310_PA_I2S1,
.end = S5PV310_PA_I2S1 + 0x100 - 1,
.start = EXYNOS4_PA_I2S1,
.end = EXYNOS4_PA_I2S1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -122,20 +125,20 @@ static struct resource s5pv310_i2s1_resource[] = {
},
};
struct platform_device s5pv310_device_i2s1 = {
struct platform_device exynos4_device_i2s1 = {
.name = "samsung-i2s",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv310_i2s1_resource),
.resource = s5pv310_i2s1_resource,
.num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
.resource = exynos4_i2s1_resource,
.dev = {
.platform_data = &i2sv3_pdata,
},
};
static struct resource s5pv310_i2s2_resource[] = {
static struct resource exynos4_i2s2_resource[] = {
[0] = {
.start = S5PV310_PA_I2S2,
.end = S5PV310_PA_I2S2 + 0x100 - 1,
.start = EXYNOS4_PA_I2S2,
.end = EXYNOS4_PA_I2S2 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -150,11 +153,11 @@ static struct resource s5pv310_i2s2_resource[] = {
},
};
struct platform_device s5pv310_device_i2s2 = {
struct platform_device exynos4_device_i2s2 = {
.name = "samsung-i2s",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv310_i2s2_resource),
.resource = s5pv310_i2s2_resource,
.num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
.resource = exynos4_i2s2_resource,
.dev = {
.platform_data = &i2sv3_pdata,
},
@ -162,17 +165,17 @@ struct platform_device s5pv310_device_i2s2 = {
/* PCM Controller platform_devices */
static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3));
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
break;
case 1:
s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3));
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
break;
case 2:
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3));
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
@ -183,13 +186,13 @@ static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5pv310_pcm_cfg_gpio,
.cfg_gpio = exynos4_pcm_cfg_gpio,
};
static struct resource s5pv310_pcm0_resource[] = {
static struct resource exynos4_pcm0_resource[] = {
[0] = {
.start = S5PV310_PA_PCM0,
.end = S5PV310_PA_PCM0 + 0x100 - 1,
.start = EXYNOS4_PA_PCM0,
.end = EXYNOS4_PA_PCM0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -204,20 +207,20 @@ static struct resource s5pv310_pcm0_resource[] = {
},
};
struct platform_device s5pv310_device_pcm0 = {
struct platform_device exynos4_device_pcm0 = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5pv310_pcm0_resource),
.resource = s5pv310_pcm0_resource,
.num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
.resource = exynos4_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5pv310_pcm1_resource[] = {
static struct resource exynos4_pcm1_resource[] = {
[0] = {
.start = S5PV310_PA_PCM1,
.end = S5PV310_PA_PCM1 + 0x100 - 1,
.start = EXYNOS4_PA_PCM1,
.end = EXYNOS4_PA_PCM1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -232,20 +235,20 @@ static struct resource s5pv310_pcm1_resource[] = {
},
};
struct platform_device s5pv310_device_pcm1 = {
struct platform_device exynos4_device_pcm1 = {
.name = "samsung-pcm",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv310_pcm1_resource),
.resource = s5pv310_pcm1_resource,
.num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
.resource = exynos4_pcm1_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5pv310_pcm2_resource[] = {
static struct resource exynos4_pcm2_resource[] = {
[0] = {
.start = S5PV310_PA_PCM2,
.end = S5PV310_PA_PCM2 + 0x100 - 1,
.start = EXYNOS4_PA_PCM2,
.end = EXYNOS4_PA_PCM2 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -260,11 +263,11 @@ static struct resource s5pv310_pcm2_resource[] = {
},
};
struct platform_device s5pv310_device_pcm2 = {
struct platform_device exynos4_device_pcm2 = {
.name = "samsung-pcm",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv310_pcm2_resource),
.resource = s5pv310_pcm2_resource,
.num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
.resource = exynos4_pcm2_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
@ -272,15 +275,15 @@ struct platform_device s5pv310_device_pcm2 = {
/* AC97 Controller platform devices */
static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev)
static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
{
return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4));
return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
}
static struct resource s5pv310_ac97_resource[] = {
static struct resource exynos4_ac97_resource[] = {
[0] = {
.start = S5PV310_PA_AC97,
.end = S5PV310_PA_AC97 + 0x100 - 1,
.start = EXYNOS4_PA_AC97,
.end = EXYNOS4_PA_AC97 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -306,36 +309,36 @@ static struct resource s5pv310_ac97_resource[] = {
};
static struct s3c_audio_pdata s3c_ac97_pdata = {
.cfg_gpio = s5pv310_ac97_cfg_gpio,
.cfg_gpio = exynos4_ac97_cfg_gpio,
};
static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32);
static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
struct platform_device s5pv310_device_ac97 = {
struct platform_device exynos4_device_ac97 = {
.name = "samsung-ac97",
.id = -1,
.num_resources = ARRAY_SIZE(s5pv310_ac97_resource),
.resource = s5pv310_ac97_resource,
.num_resources = ARRAY_SIZE(exynos4_ac97_resource),
.resource = exynos4_ac97_resource,
.dev = {
.platform_data = &s3c_ac97_pdata,
.dma_mask = &s5pv310_ac97_dmamask,
.dma_mask = &exynos4_ac97_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
/* S/PDIF Controller platform_device */
static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev)
static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
{
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3));
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
return 0;
}
static struct resource s5pv310_spdif_resource[] = {
static struct resource exynos4_spdif_resource[] = {
[0] = {
.start = S5PV310_PA_SPDIF,
.end = S5PV310_PA_SPDIF + 0x100 - 1,
.start = EXYNOS4_PA_SPDIF,
.end = EXYNOS4_PA_SPDIF + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -346,19 +349,19 @@ static struct resource s5pv310_spdif_resource[] = {
};
static struct s3c_audio_pdata samsung_spdif_pdata = {
.cfg_gpio = s5pv310_spdif_cfg_gpio,
.cfg_gpio = exynos4_spdif_cfg_gpio,
};
static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32);
static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
struct platform_device s5pv310_device_spdif = {
struct platform_device exynos4_device_spdif = {
.name = "samsung-spdif",
.id = -1,
.num_resources = ARRAY_SIZE(s5pv310_spdif_resource),
.resource = s5pv310_spdif_resource,
.num_resources = ARRAY_SIZE(exynos4_spdif_resource),
.resource = exynos4_spdif_resource,
.dev = {
.platform_data = &samsung_spdif_pdata,
.dma_mask = &s5pv310_spdif_dmamask,
.dma_mask = &exynos4_spdif_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};

40
arch/arm/mach-s5pv310/dev-pd.c → arch/arm/mach-exynos4/dev-pd.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/dev-pd.c
/* linux/arch/arm/mach-exynos4/dev-pd.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Power Domain support
* EXYNOS4 - Power Domain support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -19,7 +19,7 @@
#include <plat/pd.h>
static int s5pv310_pd_enable(struct device *dev)
static int exynos4_pd_enable(struct device *dev)
{
struct samsung_pd_info *pdata = dev->platform_data;
u32 timeout;
@ -42,7 +42,7 @@ static int s5pv310_pd_enable(struct device *dev)
return 0;
}
static int s5pv310_pd_disable(struct device *dev)
static int exynos4_pd_disable(struct device *dev)
{
struct samsung_pd_info *pdata = dev->platform_data;
u32 timeout;
@ -64,14 +64,14 @@ static int s5pv310_pd_disable(struct device *dev)
return 0;
}
struct platform_device s5pv310_device_pd[] = {
struct platform_device exynos4_device_pd[] = {
{
.name = "samsung-pd",
.id = 0,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_MFC_CONF,
},
},
@ -80,8 +80,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 1,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_G3D_CONF,
},
},
@ -90,8 +90,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 2,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_LCD0_CONF,
},
},
@ -100,8 +100,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 3,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_LCD1_CONF,
},
},
@ -110,8 +110,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 4,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_TV_CONF,
},
},
@ -120,8 +120,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 5,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_CAM_CONF,
},
},
@ -130,8 +130,8 @@ struct platform_device s5pv310_device_pd[] = {
.id = 6,
.dev = {
.platform_data = &(struct samsung_pd_info) {
.enable = s5pv310_pd_enable,
.disable = s5pv310_pd_disable,
.enable = exynos4_pd_enable,
.disable = exynos4_pd_disable,
.base = S5P_PMU_GPS_CONF,
},
},

78
arch/arm/mach-s5pv310/dev-sysmmu.c → arch/arm/mach-exynos4/dev-sysmmu.c
View File

@ -1,8 +1,10 @@
/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c
/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - System MMU support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
@ -14,10 +16,10 @@
#include <mach/map.h>
#include <mach/irqs.h>
static struct resource s5pv310_sysmmu_resource[] = {
static struct resource exynos4_sysmmu_resource[] = {
[0] = {
.start = S5PV310_PA_SYSMMU_MDMA,
.end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_MDMA,
.end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -26,8 +28,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = S5PV310_PA_SYSMMU_SSS,
.end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_SSS,
.end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[3] = {
@ -36,8 +38,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[4] = {
.start = S5PV310_PA_SYSMMU_FIMC0,
.end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMC0,
.end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[5] = {
@ -46,8 +48,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[6] = {
.start = S5PV310_PA_SYSMMU_FIMC1,
.end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMC1,
.end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[7] = {
@ -56,8 +58,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[8] = {
.start = S5PV310_PA_SYSMMU_FIMC2,
.end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMC2,
.end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[9] = {
@ -66,8 +68,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[10] = {
.start = S5PV310_PA_SYSMMU_FIMC3,
.end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMC3,
.end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[11] = {
@ -76,8 +78,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[12] = {
.start = S5PV310_PA_SYSMMU_JPEG,
.end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_JPEG,
.end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[13] = {
@ -86,8 +88,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[14] = {
.start = S5PV310_PA_SYSMMU_FIMD0,
.end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMD0,
.end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[15] = {
@ -96,8 +98,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[16] = {
.start = S5PV310_PA_SYSMMU_FIMD1,
.end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_FIMD1,
.end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[17] = {
@ -106,8 +108,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[18] = {
.start = S5PV310_PA_SYSMMU_PCIe,
.end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_PCIe,
.end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[19] = {
@ -116,8 +118,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[20] = {
.start = S5PV310_PA_SYSMMU_G2D,
.end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_G2D,
.end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[21] = {
@ -126,8 +128,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[22] = {
.start = S5PV310_PA_SYSMMU_ROTATOR,
.end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_ROTATOR,
.end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[23] = {
@ -136,8 +138,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[24] = {
.start = S5PV310_PA_SYSMMU_MDMA2,
.end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_MDMA2,
.end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[25] = {
@ -146,8 +148,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[26] = {
.start = S5PV310_PA_SYSMMU_TV,
.end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_TV,
.end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[27] = {
@ -156,8 +158,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[28] = {
.start = S5PV310_PA_SYSMMU_MFC_L,
.end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_MFC_L,
.end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[29] = {
@ -166,8 +168,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
.flags = IORESOURCE_IRQ,
},
[30] = {
.start = S5PV310_PA_SYSMMU_MFC_R,
.end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1,
.start = EXYNOS4_PA_SYSMMU_MFC_R,
.end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[31] = {
@ -177,11 +179,11 @@ static struct resource s5pv310_sysmmu_resource[] = {
},
};
struct platform_device s5pv310_device_sysmmu = {
struct platform_device exynos4_device_sysmmu = {
.name = "s5p-sysmmu",
.id = 32,
.num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource),
.resource = s5pv310_sysmmu_resource,
.num_resources = ARRAY_SIZE(exynos4_sysmmu_resource),
.resource = exynos4_sysmmu_resource,
};
EXPORT_SYMBOL(s5pv310_device_sysmmu);
EXPORT_SYMBOL(exynos4_device_sysmmu);

50
arch/arm/mach-s5pv310/dma.c → arch/arm/mach-exynos4/dma.c
View File

@ -1,4 +1,8 @@
/*
/* linux/arch/arm/mach-exynos4/dma.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
@ -30,10 +34,10 @@
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5pv310_pdma0_resource[] = {
static struct resource exynos4_pdma0_resource[] = {
[0] = {
.start = S5PV310_PA_PDMA0,
.end = S5PV310_PA_PDMA0 + SZ_4K,
.start = EXYNOS4_PA_PDMA0,
.end = EXYNOS4_PA_PDMA0 + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = {
},
};
static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
.peri = {
[0] = DMACH_PCM0_RX,
[1] = DMACH_PCM0_TX,
@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
},
};
static struct platform_device s5pv310_device_pdma0 = {
static struct platform_device exynos4_device_pdma0 = {
.name = "s3c-pl330",
.id = 0,
.num_resources = ARRAY_SIZE(s5pv310_pdma0_resource),
.resource = s5pv310_pdma0_resource,
.num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
.resource = exynos4_pdma0_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv310_pdma0_pdata,
.platform_data = &exynos4_pdma0_pdata,
},
};
static struct resource s5pv310_pdma1_resource[] = {
static struct resource exynos4_pdma1_resource[] = {
[0] = {
.start = S5PV310_PA_PDMA1,
.end = S5PV310_PA_PDMA1 + SZ_4K,
.start = EXYNOS4_PA_PDMA1,
.end = EXYNOS4_PA_PDMA1 + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = {
},
};
static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
.peri = {
[0] = DMACH_PCM0_RX,
[1] = DMACH_PCM0_TX,
@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
},
};
static struct platform_device s5pv310_device_pdma1 = {
static struct platform_device exynos4_device_pdma1 = {
.name = "s3c-pl330",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv310_pdma1_resource),
.resource = s5pv310_pdma1_resource,
.num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
.resource = exynos4_pdma1_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv310_pdma1_pdata,
.platform_data = &exynos4_pdma1_pdata,
},
};
static struct platform_device *s5pv310_dmacs[] __initdata = {
&s5pv310_device_pdma0,
&s5pv310_device_pdma1,
static struct platform_device *exynos4_dmacs[] __initdata = {
&exynos4_device_pdma0,
&exynos4_device_pdma1,
};
static int __init s5pv310_dma_init(void)
static int __init exynos4_dma_init(void)
{
platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));
platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
return 0;
}
arch_initcall(s5pv310_dma_init);
arch_initcall(exynos4_dma_init);

154
arch/arm/mach-s5pv310/gpiolib.c → arch/arm/mach-exynos4/gpiolib.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/gpiolib.c
/* linux/arch/arm/mach-exynos4/gpiolib.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - GPIOlib support
* EXYNOS4 - GPIOlib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -43,159 +43,159 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
* Note: The initialization of 'base' member of s3c_gpio_chip structure
* uses the above macro and depends on the banks being listed in order here.
*/
static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
{
.chip = {
.base = S5PV310_GPA0(0),
.ngpio = S5PV310_GPIO_A0_NR,
.base = EXYNOS4_GPA0(0),
.ngpio = EXYNOS4_GPIO_A0_NR,
.label = "GPA0",
},
}, {
.chip = {
.base = S5PV310_GPA1(0),
.ngpio = S5PV310_GPIO_A1_NR,
.base = EXYNOS4_GPA1(0),
.ngpio = EXYNOS4_GPIO_A1_NR,
.label = "GPA1",
},
}, {
.chip = {
.base = S5PV310_GPB(0),
.ngpio = S5PV310_GPIO_B_NR,
.base = EXYNOS4_GPB(0),
.ngpio = EXYNOS4_GPIO_B_NR,
.label = "GPB",
},
}, {
.chip = {
.base = S5PV310_GPC0(0),
.ngpio = S5PV310_GPIO_C0_NR,
.base = EXYNOS4_GPC0(0),
.ngpio = EXYNOS4_GPIO_C0_NR,
.label = "GPC0",
},
}, {
.chip = {
.base = S5PV310_GPC1(0),
.ngpio = S5PV310_GPIO_C1_NR,
.base = EXYNOS4_GPC1(0),
.ngpio = EXYNOS4_GPIO_C1_NR,
.label = "GPC1",
},
}, {
.chip = {
.base = S5PV310_GPD0(0),
.ngpio = S5PV310_GPIO_D0_NR,
.base = EXYNOS4_GPD0(0),
.ngpio = EXYNOS4_GPIO_D0_NR,
.label = "GPD0",
},
}, {
.chip = {
.base = S5PV310_GPD1(0),
.ngpio = S5PV310_GPIO_D1_NR,
.base = EXYNOS4_GPD1(0),
.ngpio = EXYNOS4_GPIO_D1_NR,
.label = "GPD1",
},
}, {
.chip = {
.base = S5PV310_GPE0(0),
.ngpio = S5PV310_GPIO_E0_NR,
.base = EXYNOS4_GPE0(0),
.ngpio = EXYNOS4_GPIO_E0_NR,
.label = "GPE0",
},
}, {
.chip = {
.base = S5PV310_GPE1(0),
.ngpio = S5PV310_GPIO_E1_NR,
.base = EXYNOS4_GPE1(0),
.ngpio = EXYNOS4_GPIO_E1_NR,
.label = "GPE1",
},
}, {
.chip = {
.base = S5PV310_GPE2(0),
.ngpio = S5PV310_GPIO_E2_NR,
.base = EXYNOS4_GPE2(0),
.ngpio = EXYNOS4_GPIO_E2_NR,
.label = "GPE2",
},
}, {
.chip = {
.base = S5PV310_GPE3(0),
.ngpio = S5PV310_GPIO_E3_NR,
.base = EXYNOS4_GPE3(0),
.ngpio = EXYNOS4_GPIO_E3_NR,
.label = "GPE3",
},
}, {
.chip = {
.base = S5PV310_GPE4(0),
.ngpio = S5PV310_GPIO_E4_NR,
.base = EXYNOS4_GPE4(0),
.ngpio = EXYNOS4_GPIO_E4_NR,
.label = "GPE4",
},
}, {
.chip = {
.base = S5PV310_GPF0(0),
.ngpio = S5PV310_GPIO_F0_NR,
.base = EXYNOS4_GPF0(0),
.ngpio = EXYNOS4_GPIO_F0_NR,
.label = "GPF0",
},
}, {
.chip = {
.base = S5PV310_GPF1(0),
.ngpio = S5PV310_GPIO_F1_NR,
.base = EXYNOS4_GPF1(0),
.ngpio = EXYNOS4_GPIO_F1_NR,
.label = "GPF1",
},
}, {
.chip = {
.base = S5PV310_GPF2(0),
.ngpio = S5PV310_GPIO_F2_NR,
.base = EXYNOS4_GPF2(0),
.ngpio = EXYNOS4_GPIO_F2_NR,
.label = "GPF2",
},
}, {
.chip = {
.base = S5PV310_GPF3(0),
.ngpio = S5PV310_GPIO_F3_NR,
.base = EXYNOS4_GPF3(0),
.ngpio = EXYNOS4_GPIO_F3_NR,
.label = "GPF3",
},
},
};
static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
{
.chip = {
.base = S5PV310_GPJ0(0),
.ngpio = S5PV310_GPIO_J0_NR,
.base = EXYNOS4_GPJ0(0),
.ngpio = EXYNOS4_GPIO_J0_NR,
.label = "GPJ0",
},
}, {
.chip = {
.base = S5PV310_GPJ1(0),
.ngpio = S5PV310_GPIO_J1_NR,
.base = EXYNOS4_GPJ1(0),
.ngpio = EXYNOS4_GPIO_J1_NR,
.label = "GPJ1",
},
}, {
.chip = {
.base = S5PV310_GPK0(0),
.ngpio = S5PV310_GPIO_K0_NR,
.base = EXYNOS4_GPK0(0),
.ngpio = EXYNOS4_GPIO_K0_NR,
.label = "GPK0",
},
}, {
.chip = {
.base = S5PV310_GPK1(0),
.ngpio = S5PV310_GPIO_K1_NR,
.base = EXYNOS4_GPK1(0),
.ngpio = EXYNOS4_GPIO_K1_NR,
.label = "GPK1",
},
}, {
.chip = {
.base = S5PV310_GPK2(0),
.ngpio = S5PV310_GPIO_K2_NR,
.base = EXYNOS4_GPK2(0),
.ngpio = EXYNOS4_GPIO_K2_NR,
.label = "GPK2",
},
}, {
.chip = {
.base = S5PV310_GPK3(0),
.ngpio = S5PV310_GPIO_K3_NR,
.base = EXYNOS4_GPK3(0),
.ngpio = EXYNOS4_GPIO_K3_NR,
.label = "GPK3",
},
}, {
.chip = {
.base = S5PV310_GPL0(0),
.ngpio = S5PV310_GPIO_L0_NR,
.base = EXYNOS4_GPL0(0),
.ngpio = EXYNOS4_GPIO_L0_NR,
.label = "GPL0",
},
}, {
.chip = {
.base = S5PV310_GPL1(0),
.ngpio = S5PV310_GPIO_L1_NR,
.base = EXYNOS4_GPL1(0),
.ngpio = EXYNOS4_GPIO_L1_NR,
.label = "GPL1",
},
}, {
.chip = {
.base = S5PV310_GPL2(0),
.ngpio = S5PV310_GPIO_L2_NR,
.base = EXYNOS4_GPL2(0),
.ngpio = EXYNOS4_GPIO_L2_NR,
.label = "GPL2",
},
}, {
@ -203,8 +203,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(0),
.chip = {
.base = S5PV310_GPX0(0),
.ngpio = S5PV310_GPIO_X0_NR,
.base = EXYNOS4_GPX0(0),
.ngpio = EXYNOS4_GPIO_X0_NR,
.label = "GPX0",
.to_irq = samsung_gpiolib_to_irq,
},
@ -213,8 +213,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(8),
.chip = {
.base = S5PV310_GPX1(0),
.ngpio = S5PV310_GPIO_X1_NR,
.base = EXYNOS4_GPX1(0),
.ngpio = EXYNOS4_GPIO_X1_NR,
.label = "GPX1",
.to_irq = samsung_gpiolib_to_irq,
},
@ -223,8 +223,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(16),
.chip = {
.base = S5PV310_GPX2(0),
.ngpio = S5PV310_GPIO_X2_NR,
.base = EXYNOS4_GPX2(0),
.ngpio = EXYNOS4_GPIO_X2_NR,
.label = "GPX2",
.to_irq = samsung_gpiolib_to_irq,
},
@ -233,25 +233,25 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
.config = &gpio_cfg_noint,
.irq_base = IRQ_EINT(24),
.chip = {
.base = S5PV310_GPX3(0),
.ngpio = S5PV310_GPIO_X3_NR,
.base = EXYNOS4_GPX3(0),
.ngpio = EXYNOS4_GPIO_X3_NR,
.label = "GPX3",
.to_irq = samsung_gpiolib_to_irq,
},
},
};
static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
{
.chip = {
.base = S5PV310_GPZ(0),
.ngpio = S5PV310_GPIO_Z_NR,
.base = EXYNOS4_GPZ(0),
.ngpio = EXYNOS4_GPIO_Z_NR,
.label = "GPZ",
},
},
};
static __init int s5pv310_gpiolib_init(void)
static __init int exynos4_gpiolib_init(void)
{
struct s3c_gpio_chip *chip;
int i;
@ -259,8 +259,8 @@ static __init int s5pv310_gpiolib_init(void)
/* GPIO part 1 */
chip = s5pv310_gpio_part1_4bit;
nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
chip = exynos4_gpio_part1_4bit;
nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL)
@ -269,12 +269,12 @@ static __init int s5pv310_gpiolib_init(void)
chip->base = S5P_VA_GPIO1 + (i) * 0x20;
}
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
/* GPIO part 2 */
chip = s5pv310_gpio_part2_4bit;
nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
chip = exynos4_gpio_part2_4bit;
nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL)
@ -283,12 +283,12 @@ static __init int s5pv310_gpiolib_init(void)
chip->base = S5P_VA_GPIO2 + (i) * 0x20;
}
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
/* GPIO part 3 */
chip = s5pv310_gpio_part3_4bit;
nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
chip = exynos4_gpio_part3_4bit;
nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
for (i = 0; i < nr_chips; i++, chip++) {
if (chip->config == NULL)
@ -297,8 +297,8 @@ static __init int s5pv310_gpiolib_init(void)
chip->base = S5P_VA_GPIO3 + (i) * 0x20;
}
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
return 0;
}
core_initcall(s5pv310_gpiolib_init);
core_initcall(exynos4_gpiolib_init);

6
arch/arm/mach-s5pv310/headsmp.S → arch/arm/mach-exynos4/headsmp.S
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-s5pv310/headsmp.S
* linux/arch/arm/mach-exynos4/headsmp.S
*
* Cloned from linux/arch/arm/mach-realview/headsmp.S
*
@ -16,11 +16,11 @@
__INIT
/*
* s5pv310 specific entry point for secondary CPUs. This provides
* exynos4 specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
* ready for them to initialise.
*/
ENTRY(s5pv310_secondary_startup)
ENTRY(exynos4_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f

10
arch/arm/mach-s5pv310/hotplug.c → arch/arm/mach-exynos4/hotplug.c
View File

@ -1,4 +1,4 @@
/* linux arch/arm/mach-s5pv310/hotplug.c
/* linux arch/arm/mach-exynos4/hotplug.c
*
* Cloned from linux/arch/arm/mach-realview/hotplug.c
*
@ -30,13 +30,13 @@ static inline void cpu_enter_lowpower(void)
* Turn off coherency
*/
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, #0x20\n"
" bic %0, %0, %3\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0), "Ir" (CR_C)
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
: "cc");
}
@ -49,10 +49,10 @@ static inline void cpu_leave_lowpower(void)
" orr %0, %0, %1\n"
" mcr p15, 0, %0, c1, c0, 0\n"
" mrc p15, 0, %0, c1, c0, 1\n"
" orr %0, %0, #0x20\n"
" orr %0, %0, %2\n"
" mcr p15, 0, %0, c1, c0, 1\n"
: "=&r" (v)
: "Ir" (CR_C)
: "Ir" (CR_C), "Ir" (0x40)
: "cc");
}

6
arch/arm/mach-s5pv310/include/mach/debug-macro.S → arch/arm/mach-exynos4/include/mach/debug-macro.S
View File

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S
/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
*

0
arch/arm/mach-s5pv310/include/mach/dma.h → arch/arm/mach-exynos4/include/mach/dma.h
View File

4
arch/arm/mach-s5pv310/include/mach/entry-macro.S → arch/arm/mach-exynos4/include/mach/entry-macro.S
View File

@ -1,8 +1,8 @@
/* arch/arm/mach-s5pv310/include/mach/entry-macro.S
/* arch/arm/mach-exynos4/include/mach/entry-macro.S
*
* Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for S5PV310 platforms
* Low-level IRQ helper macros for EXYNOS4 platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any

135
arch/arm/mach-exynos4/include/mach/gpio.h Normal file
View File

@ -0,0 +1,135 @@
/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
/* GPIO bank sizes */
#define EXYNOS4_GPIO_A0_NR (8)
#define EXYNOS4_GPIO_A1_NR (6)
#define EXYNOS4_GPIO_B_NR (8)
#define EXYNOS4_GPIO_C0_NR (5)
#define EXYNOS4_GPIO_C1_NR (5)
#define EXYNOS4_GPIO_D0_NR (4)
#define EXYNOS4_GPIO_D1_NR (4)
#define EXYNOS4_GPIO_E0_NR (5)
#define EXYNOS4_GPIO_E1_NR (8)
#define EXYNOS4_GPIO_E2_NR (6)
#define EXYNOS4_GPIO_E3_NR (8)
#define EXYNOS4_GPIO_E4_NR (8)
#define EXYNOS4_GPIO_F0_NR (8)
#define EXYNOS4_GPIO_F1_NR (8)
#define EXYNOS4_GPIO_F2_NR (8)
#define EXYNOS4_GPIO_F3_NR (6)
#define EXYNOS4_GPIO_J0_NR (8)
#define EXYNOS4_GPIO_J1_NR (5)
#define EXYNOS4_GPIO_K0_NR (7)
#define EXYNOS4_GPIO_K1_NR (7)
#define EXYNOS4_GPIO_K2_NR (7)
#define EXYNOS4_GPIO_K3_NR (7)
#define EXYNOS4_GPIO_L0_NR (8)
#define EXYNOS4_GPIO_L1_NR (3)
#define EXYNOS4_GPIO_L2_NR (8)
#define EXYNOS4_GPIO_X0_NR (8)
#define EXYNOS4_GPIO_X1_NR (8)
#define EXYNOS4_GPIO_X2_NR (8)
#define EXYNOS4_GPIO_X3_NR (8)
#define EXYNOS4_GPIO_Z_NR (7)
/* GPIO bank numbers */
#define EXYNOS4_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s5p_gpio_number {
EXYNOS4_GPIO_A0_START = 0,
EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
};
/* EXYNOS4 GPIO number definitions */
#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
/* the end of the EXYNOS4 specific gpios */
#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
#define S3C_GPIO_END EXYNOS4_GPIO_END
/* define the number of gpios we need to the one after the GPZ() range */
#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */

8
arch/arm/mach-s5pv310/include/mach/hardware.h → arch/arm/mach-exynos4/include/mach/hardware.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h
/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Hardware support
* EXYNOS4 - Hardware support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

8
arch/arm/mach-s5pv310/include/mach/io.h → arch/arm/mach-exynos4/include/mach/io.h
View File

@ -1,13 +1,13 @@
/* linux/arch/arm/mach-s5pv310/include/mach/io.h
/* linux/arch/arm/mach-exynos4/include/mach/io.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
*
* Based on arch/arm/mach-s5p6442/include/mach/io.h
*
* Default IO routines for S5PV310
* Default IO routines for EXYNOS4
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

9
arch/arm/mach-s5pv310/include/mach/irqs.h → arch/arm/mach-exynos4/include/mach/irqs.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h
/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - IRQ definitions
* EXYNOS4 - IRQ definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -131,6 +131,7 @@
#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
#define IRQ_WDT COMBINER_IRQ(53, 0)
#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
#define MAX_COMBINER_NR 54

145
arch/arm/mach-exynos4/include/mach/map.h Normal file
View File

@ -0,0 +1,145 @@
/* linux/arch/arm/mach-exynos4/include/mach/map.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* EXYNOS4 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
/*
* EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
* So need to define it, and here is to avoid redefinition warning.
*/
#define S3C_UART_OFFSET (0x10000)
#include <plat/map-s5p.h>
#define EXYNOS4_PA_SYSRAM 0x02020000
#define EXYNOS4_PA_I2S0 0x03830000
#define EXYNOS4_PA_I2S1 0xE3100000
#define EXYNOS4_PA_I2S2 0xE2A00000
#define EXYNOS4_PA_PCM0 0x03840000
#define EXYNOS4_PA_PCM1 0x13980000
#define EXYNOS4_PA_PCM2 0x13990000
#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
#define EXYNOS4_PA_ONENAND 0x0C000000
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
#define EXYNOS4_PA_CHIPID 0x10000000
#define EXYNOS4_PA_SYSCON 0x10010000
#define EXYNOS4_PA_PMU 0x10020000
#define EXYNOS4_PA_CMU 0x10030000
#define EXYNOS4_PA_SYSTIMER 0x10050000
#define EXYNOS4_PA_WATCHDOG 0x10060000
#define EXYNOS4_PA_RTC 0x10070000
#define EXYNOS4_PA_DMC0 0x10400000
#define EXYNOS4_PA_COMBINER 0x10448000
#define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_GIC_CPU 0x10500100
#define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_GIC_DIST 0x10501000
#define EXYNOS4_PA_L2CC 0x10502000
#define EXYNOS4_PA_MDMA 0x10810000
#define EXYNOS4_PA_PDMA0 0x12680000
#define EXYNOS4_PA_PDMA1 0x12690000
#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
#define EXYNOS4_PA_GPIO1 0x11400000
#define EXYNOS4_PA_GPIO2 0x11000000
#define EXYNOS4_PA_GPIO3 0x03860000
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define EXYNOS4_PA_SROMC 0x12570000
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define EXYNOS4_PA_AC97 0x139A0000
#define EXYNOS4_PA_SPDIF 0x139B0000
#define EXYNOS4_PA_TIMER 0x139D0000
#define EXYNOS4_PA_SDRAM 0x40000000
/* Compatibiltiy Defines */
#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
#define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
#define S5P_PA_SROMC EXYNOS4_PA_SROMC
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
/* UART */
#define S3C_PA_UART EXYNOS4_PA_UART
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#define S5P_PA_UART4 S5P_PA_UART(4)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

8
arch/arm/mach-s5pv310/include/mach/memory.h → arch/arm/mach-exynos4/include/mach/memory.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/memory.h
/* linux/arch/arm/mach-exynos4/include/mach/memory.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Memory definitions
* EXYNOS4 - Memory definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

8
arch/arm/mach-s5pv310/include/mach/pwm-clock.h → arch/arm/mach-exynos4/include/mach/pwm-clock.h
View File

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
@ -10,7 +10,7 @@
*
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
*
* S5PV310 - pwm clock and timer support
* EXYNOS4 - pwm clock and timer support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

8
arch/arm/mach-s5pv310/include/mach/regs-clock.h → arch/arm/mach-exynos4/include/mach/regs-clock.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Clock register definitions
* EXYNOS4 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

42
arch/arm/mach-exynos4/include/mach/regs-gpio.h Normal file
View File

@ -0,0 +1,42 @@
/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - GPIO (including EINT) register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H __FILE__
#include <mach/map.h>
#include <mach/irqs.h>
#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
#define EINT_MODE S3C_GPIO_SFN(0xf)
#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
#endif /* __ASM_ARCH_REGS_GPIO_H */

8
arch/arm/mach-s5pv310/include/mach/regs-irq.h → arch/arm/mach-exynos4/include/mach/regs-irq.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h
/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - IRQ register definitions
* EXYNOS4 - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

52
arch/arm/mach-exynos4/include/mach/regs-mct.h Normal file
View File

@ -0,0 +1,52 @@
/* arch/arm/mach-exynos4/include/mach/regs-mct.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 MCT configutation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_MCT_H
#define __ASM_ARCH_REGS_MCT_H __FILE__
#include <mach/map.h>
#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
#define EXYNOS4_MCT_L0_BASE EXYNOS4_MCTREG(0x300)
#define EXYNOS4_MCT_L1_BASE EXYNOS4_MCTREG(0x400)
#define MCT_L_TCNTB_OFFSET (0x00)
#define MCT_L_ICNTB_OFFSET (0x08)
#define MCT_L_TCON_OFFSET (0x20)
#define MCT_L_INT_CSTAT_OFFSET (0x30)
#define MCT_L_INT_ENB_OFFSET (0x34)
#define MCT_L_WSTAT_OFFSET (0x40)
#define MCT_G_TCON_START (1 << 8)
#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
#define MCT_L_TCON_INT_START (1 << 1)
#define MCT_L_TCON_TIMER_START (1 << 0)
#endif /* __ASM_ARCH_REGS_MCT_H */

6
arch/arm/mach-s5pv310/include/mach/regs-mem.h → arch/arm/mach-exynos4/include/mach/regs-mem.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h
/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - SROMC and DMC register definitions
* EXYNOS4 - SROMC and DMC register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

8
arch/arm/mach-s5pv310/include/mach/regs-pmu.h → arch/arm/mach-exynos4/include/mach/regs-pmu.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Power management unit definition
* EXYNOS4 - Power management unit definition
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -18,7 +18,7 @@
#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)

6
arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h → arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - System MMU register
* EXYNOS4 - System MMU register
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

2
arch/arm/mach-s5pv310/include/mach/smp.h → arch/arm/mach-exynos4/include/mach/smp.h
View File

@ -1,4 +1,4 @@
/* linux/arch/arm/mach-s5pv310/include/mach/smp.h
/* linux/arch/arm/mach-exynos4/include/mach/smp.h
*
* Cloned from arch/arm/mach-realview/include/mach/smp.h
*/

18
arch/arm/mach-s5pv310/include/mach/sysmmu.h → arch/arm/mach-exynos4/include/mach/sysmmu.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h
/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung sysmmu driver for S5PV310
* Samsung sysmmu driver for EXYNOS4
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -13,10 +13,10 @@
#ifndef __ASM_ARM_ARCH_SYSMMU_H
#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
#define S5PV310_SYSMMU_TOTAL_IPNUM 16
#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM
#define EXYNOS4_SYSMMU_TOTAL_IPNUM 16
#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM
enum s5pv310_sysmmu_ips {
enum exynos4_sysmmu_ips {
SYSMMU_MDMA,
SYSMMU_SSS,
SYSMMU_FIMC0,
@ -35,7 +35,7 @@ enum s5pv310_sysmmu_ips {
SYSMMU_MFC_R,
};
static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
static char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
"SYSMMU_MDMA" ,
"SYSMMU_SSS" ,
"SYSMMU_FIMC0" ,
@ -54,7 +54,7 @@ static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
"SYSMMU_MFC_R" ,
};
typedef enum s5pv310_sysmmu_ips sysmmu_ips;
typedef enum exynos4_sysmmu_ips sysmmu_ips;
struct sysmmu_tt_info {
unsigned long *pgd;

8
arch/arm/mach-s5pv310/include/mach/system.h → arch/arm/mach-exynos4/include/mach/system.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/system.h
/* linux/arch/arm/mach-exynos4/include/mach/system.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - system support header
* EXYNOS4 - system support header
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

8
arch/arm/mach-s5pv310/include/mach/timex.h → arch/arm/mach-exynos4/include/mach/timex.h
View File

@ -1,14 +1,14 @@
/* linux/arch/arm/mach-s5pv310/include/mach/timex.h
/* linux/arch/arm/mach-exynos4/include/mach/timex.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (c) 2003-2010 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Based on arch/arm/mach-s5p6442/include/mach/timex.h
*
* S5PV310 - time parameters
* EXYNOS4 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

8
arch/arm/mach-s5pv310/include/mach/uncompress.h → arch/arm/mach-exynos4/include/mach/uncompress.h
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h
/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - uncompress code
* EXYNOS4 - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as

8
arch/arm/mach-s5pv310/include/mach/vmalloc.h → arch/arm/mach-exynos4/include/mach/vmalloc.h
View File

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h
/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2010 Ben Dooks <ben-linux@fluff.org>
*
@ -11,7 +11,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* S5PV310 vmalloc definition
* EXYNOS4 vmalloc definition
*/
#ifndef __ASM_ARCH_VMALLOC_H

10
arch/arm/mach-s5pv310/init.c → arch/arm/mach-exynos4/init.c
View File

@ -1,4 +1,4 @@
/* linux/arch/arm/mach-s5pv310/init.c
/* linux/arch/arm/mach-exynos4/init.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
@ -14,7 +14,7 @@
#include <plat/devs.h>
#include <plat/regs-serial.h>
static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
[0] = {
.name = "uclk1",
.divisor = 1,
@ -24,7 +24,7 @@ static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
};
/* uart registration process */
void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
{
struct s3c2410_uartcfg *tcfg = cfg;
u32 ucnt;
@ -32,8 +32,8 @@ void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
if (!tcfg->clocks) {
tcfg->has_fracval = 1;
tcfg->clocks = s5pv310_serial_clocks;
tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks);
tcfg->clocks = exynos4_serial_clocks;
tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
}
}

4
arch/arm/mach-s5pv310/irq-combiner.c → arch/arm/mach-exynos4/irq-combiner.c
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s5pv310/irq-combiner.c
/* linux/arch/arm/mach-exynos4/irq-combiner.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Based on arch/arm/common/gic.c

62
arch/arm/mach-s5pv310/irq-eint.c → arch/arm/mach-exynos4/irq-eint.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/irq-eint.c
/* linux/arch/arm/mach-exynos4/irq-eint.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - IRQ EINT support
* EXYNOS4 - IRQ EINT support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -27,7 +27,7 @@ static DEFINE_SPINLOCK(eint_lock);
static unsigned int eint0_15_data[16];
static unsigned int s5pv310_get_irq_nr(unsigned int number)
static unsigned int exynos4_get_irq_nr(unsigned int number)
{
u32 ret = 0;
@ -48,7 +48,7 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
return ret;
}
static inline void s5pv310_irq_eint_mask(struct irq_data *data)
static inline void exynos4_irq_eint_mask(struct irq_data *data)
{
u32 mask;
@ -59,7 +59,7 @@ static inline void s5pv310_irq_eint_mask(struct irq_data *data)
spin_unlock(&eint_lock);
}
static void s5pv310_irq_eint_unmask(struct irq_data *data)
static void exynos4_irq_eint_unmask(struct irq_data *data)
{
u32 mask;
@ -70,19 +70,19 @@ static void s5pv310_irq_eint_unmask(struct irq_data *data)
spin_unlock(&eint_lock);
}
static inline void s5pv310_irq_eint_ack(struct irq_data *data)
static inline void exynos4_irq_eint_ack(struct irq_data *data)
{
__raw_writel(eint_irq_to_bit(data->irq),
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
}
static void s5pv310_irq_eint_maskack(struct irq_data *data)
static void exynos4_irq_eint_maskack(struct irq_data *data)
{
s5pv310_irq_eint_mask(data);
s5pv310_irq_eint_ack(data);
exynos4_irq_eint_mask(data);
exynos4_irq_eint_ack(data);
}
static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
{
int offs = EINT_OFFSET(data->irq);
int shift;
@ -145,19 +145,19 @@ static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
return 0;
}
static struct irq_chip s5pv310_irq_eint = {
.name = "s5pv310-eint",
.irq_mask = s5pv310_irq_eint_mask,
.irq_unmask = s5pv310_irq_eint_unmask,
.irq_mask_ack = s5pv310_irq_eint_maskack,
.irq_ack = s5pv310_irq_eint_ack,
.irq_set_type = s5pv310_irq_eint_set_type,
static struct irq_chip exynos4_irq_eint = {
.name = "exynos4-eint",
.irq_mask = exynos4_irq_eint_mask,
.irq_unmask = exynos4_irq_eint_unmask,
.irq_mask_ack = exynos4_irq_eint_maskack,
.irq_ack = exynos4_irq_eint_ack,
.irq_set_type = exynos4_irq_eint_set_type,
#ifdef CONFIG_PM
.irq_set_wake = s3c_irqext_wake,
#endif
};
/* s5pv310_irq_demux_eint
/* exynos4_irq_demux_eint
*
* This function demuxes the IRQ from from EINTs 16 to 31.
* It is designed to be inlined into the specific handler
@ -165,7 +165,7 @@ static struct irq_chip s5pv310_irq_eint = {
*
* Each EINT pend/mask registers handle eight of them.
*/
static inline void s5pv310_irq_demux_eint(unsigned int start)
static inline void exynos4_irq_demux_eint(unsigned int start)
{
unsigned int irq;
@ -182,13 +182,13 @@ static inline void s5pv310_irq_demux_eint(unsigned int start)
}
}
static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
{
s5pv310_irq_demux_eint(IRQ_EINT(16));
s5pv310_irq_demux_eint(IRQ_EINT(24));
exynos4_irq_demux_eint(IRQ_EINT(16));
exynos4_irq_demux_eint(IRQ_EINT(24));
}
static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
u32 *irq_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq);
@ -203,27 +203,27 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
chip->irq_unmask(&desc->irq_data);
}
int __init s5pv310_init_irq_eint(void)
int __init exynos4_init_irq_eint(void)
{
int irq;
for (irq = 0 ; irq <= 31 ; irq++) {
set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
set_irq_handler(IRQ_EINT(irq), handle_level_irq);
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
}
set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
for (irq = 0 ; irq <= 15 ; irq++) {
eint0_15_data[irq] = IRQ_EINT(irq);
set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]);
set_irq_chained_handler(s5pv310_get_irq_nr(irq),
s5pv310_irq_eint0_15);
set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
set_irq_chained_handler(exynos4_get_irq_nr(irq),
exynos4_irq_eint0_15);
}
return 0;
}
arch_initcall(s5pv310_init_irq_eint);
arch_initcall(exynos4_init_irq_eint);

2
arch/arm/mach-s5pv310/localtimer.c → arch/arm/mach-exynos4/localtimer.c
View File

@ -1,4 +1,4 @@
/* linux/arch/arm/mach-s5pv310/localtimer.c
/* linux/arch/arm/mach-exynos4/localtimer.c
*
* Cloned from linux/arch/arm/mach-realview/localtimer.c
*

214
arch/arm/mach-exynos4/mach-armlex4210.c Normal file
View File

@ -0,0 +1,214 @@
/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/smsc911x.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/exynos4.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/sdhci.h>
#include <mach/map.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG4 | \
S5PV210_UFCON_RXTRIG4)
static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.flags = 0,
.ucon = ARMLEX4210_UCON_DEFAULT,
.ulcon = ARMLEX4210_ULCON_DEFAULT,
.ufcon = ARMLEX4210_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.flags = 0,
.ucon = ARMLEX4210_UCON_DEFAULT,
.ulcon = ARMLEX4210_ULCON_DEFAULT,
.ufcon = ARMLEX4210_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.flags = 0,
.ucon = ARMLEX4210_UCON_DEFAULT,
.ulcon = ARMLEX4210_ULCON_DEFAULT,
.ufcon = ARMLEX4210_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.flags = 0,
.ucon = ARMLEX4210_UCON_DEFAULT,
.ulcon = ARMLEX4210_ULCON_DEFAULT,
.ufcon = ARMLEX4210_UFCON_DEFAULT,
},
};
static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
#endif
};
static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = EXYNOS4_GPX2(5),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
.max_width = 4,
};
static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
.max_width = 4,
};
static void __init armlex4210_sdhci_init(void)
{
s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
}
static void __init armlex4210_wlan_init(void)
{
/* enable */
s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
/* reset */
s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
/* wakeup */
s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
}
static struct resource armlex4210_smsc911x_resources[] = {
[0] = {
.start = EXYNOS4_PA_SROM_BANK(3),
.end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_EINT(27),
.end = IRQ_EINT(27),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
},
};
static struct smsc911x_platform_config smsc9215_config = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
.phy_interface = PHY_INTERFACE_MODE_MII,
.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
};
static struct platform_device armlex4210_smsc911x = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
.resource = armlex4210_smsc911x_resources,
.dev = {
.platform_data = &smsc9215_config,
},
};
static struct platform_device *armlex4210_devices[] __initdata = {
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_rtc,
&s3c_device_wdt,
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&armlex4210_smsc911x,
};
static void __init armlex4210_smsc911x_init(void)
{
u32 cs1;
/* configure nCS1 width to 16 bits */
cs1 = __raw_readl(S5P_SROM_BW) &
~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
(0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
(1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
S5P_SROM_BW__NCS1__SHIFT;
__raw_writel(cs1, S5P_SROM_BW);
/* set timing for nCS1 suitable for ethernet chip */
__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
(0x9 << S5P_SROM_BCX__TACP__SHIFT) |
(0xc << S5P_SROM_BCX__TCAH__SHIFT) |
(0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
(0x6 << S5P_SROM_BCX__TACC__SHIFT) |
(0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}
static void __init armlex4210_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(armlex4210_uartcfgs,
ARRAY_SIZE(armlex4210_uartcfgs));
}
static void __init armlex4210_machine_init(void)
{
armlex4210_smsc911x_init();
armlex4210_sdhci_init();
armlex4210_wlan_init();
platform_add_devices(armlex4210_devices,
ARRAY_SIZE(armlex4210_devices));
}
MACHINE_START(ARMLEX4210, "ARMLEX4210")
/* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = exynos4_init_irq,
.map_io = armlex4210_map_io,
.init_machine = armlex4210_machine_init,
.timer = &exynos4_timer,
MACHINE_END

305
arch/arm/mach-exynos4/mach-nuri.c Normal file
View File

@ -0,0 +1,305 @@
/*
* linux/arch/arm/mach-exynos4/mach-nuri.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/mmc/host.h>
#include <linux/fb.h>
#include <linux/pwm_backlight.h>
#include <video/platform_lcd.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
#include <mach/map.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define NURI_ULCON_DEFAULT S3C2410_LCON_CS8
#define NURI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG256 | \
S5PV210_UFCON_RXTRIG256)
enum fixed_regulator_id {
FIXED_REG_ID_MMC = 0,
};
static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
{
.hwport = 0,
.ucon = NURI_UCON_DEFAULT,
.ulcon = NURI_ULCON_DEFAULT,
.ufcon = NURI_UFCON_DEFAULT,
},
{
.hwport = 1,
.ucon = NURI_UCON_DEFAULT,
.ulcon = NURI_ULCON_DEFAULT,
.ufcon = NURI_UFCON_DEFAULT,
},
{
.hwport = 2,
.ucon = NURI_UCON_DEFAULT,
.ulcon = NURI_ULCON_DEFAULT,
.ufcon = NURI_UFCON_DEFAULT,
},
{
.hwport = 3,
.ucon = NURI_UCON_DEFAULT,
.ulcon = NURI_ULCON_DEFAULT,
.ufcon = NURI_UFCON_DEFAULT,
},
};
/* eMMC */
static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE | MMC_CAP_ERASE),
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply emmc_supplies[] = {
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
REGULATOR_SUPPLY("vmmc", "dw_mmc"),
};
static struct regulator_init_data emmc_fixed_voltage_init_data = {
.constraints = {
.name = "VMEM_VDD_2.8V",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(emmc_supplies),
.consumer_supplies = emmc_supplies,
};
static struct fixed_voltage_config emmc_fixed_voltage_config = {
.supply_name = "MASSMEMORY_EN (inverted)",
.microvolts = 2800000,
.gpio = EXYNOS4_GPL1(1),
.enable_high = false,
.init_data = &emmc_fixed_voltage_init_data,
};
static struct platform_device emmc_fixed_voltage = {
.name = "reg-fixed-voltage",
.id = FIXED_REG_ID_MMC,
.dev = {
.platform_data = &emmc_fixed_voltage_config,
},
};
/* SD */
static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE,
.ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */
.ext_cd_gpio_invert = 1,
.cd_type = S3C_SDHCI_CD_GPIO,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* WLAN */
static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
.cd_type = S3C_SDHCI_CD_EXTERNAL,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static void __init nuri_sdhci_init(void)
{
s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
}
/* GPIO KEYS */
static struct gpio_keys_button nuri_gpio_keys_tables[] = {
{
.code = KEY_VOLUMEUP,
.gpio = EXYNOS4_GPX2(0), /* XEINT16 */
.desc = "gpio-keys: KEY_VOLUMEUP",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_VOLUMEDOWN,
.gpio = EXYNOS4_GPX2(1), /* XEINT17 */
.desc = "gpio-keys: KEY_VOLUMEDOWN",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_POWER,
.gpio = EXYNOS4_GPX2(7), /* XEINT23 */
.desc = "gpio-keys: KEY_POWER",
.type = EV_KEY,
.active_low = 1,
.wakeup = 1,
.debounce_interval = 1,
},
};
static struct gpio_keys_platform_data nuri_gpio_keys_data = {
.buttons = nuri_gpio_keys_tables,
.nbuttons = ARRAY_SIZE(nuri_gpio_keys_tables),
};
static struct platform_device nuri_gpio_keys = {
.name = "gpio-keys",
.dev = {
.platform_data = &nuri_gpio_keys_data,
},
};
static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
{
int gpio = EXYNOS4_GPE1(5);
gpio_request(gpio, "LVDS_nSHDN");
gpio_direction_output(gpio, power);
gpio_free(gpio);
}
static int nuri_bl_init(struct device *dev)
{
int ret, gpio = EXYNOS4_GPE2(3);
ret = gpio_request(gpio, "LCD_LDO_EN");
if (!ret)
gpio_direction_output(gpio, 0);
return ret;
}
static int nuri_bl_notify(struct device *dev, int brightness)
{
if (brightness < 1)
brightness = 0;
gpio_set_value(EXYNOS4_GPE2(3), 1);
return brightness;
}
static void nuri_bl_exit(struct device *dev)
{
gpio_free(EXYNOS4_GPE2(3));
}
/* nuri pwm backlight */
static struct platform_pwm_backlight_data nuri_backlight_data = {
.pwm_id = 0,
.pwm_period_ns = 30000,
.max_brightness = 100,
.dft_brightness = 50,
.init = nuri_bl_init,
.notify = nuri_bl_notify,
.exit = nuri_bl_exit,
};
static struct platform_device nuri_backlight_device = {
.name = "pwm-backlight",
.id = -1,
.dev = {
.parent = &s3c_device_timer[0].dev,
.platform_data = &nuri_backlight_data,
},
};
static struct plat_lcd_data nuri_lcd_platform_data = {
.set_power = nuri_lcd_power_on,
};
static struct platform_device nuri_lcd_device = {
.name = "platform-lcd",
.id = -1,
.dev = {
.platform_data = &nuri_lcd_platform_data,
},
};
/* I2C1 */
static struct i2c_board_info i2c1_devs[] __initdata = {
/* Gyro, To be updated */
};
/* GPIO I2C 5 (PMIC) */
static struct i2c_board_info i2c5_devs[] __initdata = {
/* max8997, To be updated */
};
static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
&emmc_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_wdt,
&s3c_device_timer[0],
/* NURI Devices */
&nuri_gpio_keys,
&nuri_lcd_device,
&nuri_backlight_device,
};
static void __init nuri_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
}
static void __init nuri_machine_init(void)
{
nuri_sdhci_init();
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
}
MACHINE_START(NURI, "NURI")
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = exynos4_init_irq,
.map_io = nuri_map_io,
.init_machine = nuri_machine_init,
.timer = &exynos4_timer,
MACHINE_END

48
arch/arm/mach-s5pv310/mach-smdkc210.c → arch/arm/mach-exynos4/mach-smdkc210.c
View File

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c
/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -21,7 +21,7 @@
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/s5pv310.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
@ -77,10 +77,10 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = S5PV310_GPK0(2),
.ext_cd_gpio = EXYNOS4_GPK0(2),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
#endif
@ -88,17 +88,17 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = S5PV310_GPK0(2),
.ext_cd_gpio = EXYNOS4_GPK0(2),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = S5PV310_GPK2(2),
.ext_cd_gpio = EXYNOS4_GPK2(2),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
#endif
@ -106,15 +106,15 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = S5PV310_GPK2(2),
.ext_cd_gpio = EXYNOS4_GPK2(2),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct resource smdkc210_smsc911x_resources[] = {
[0] = {
.start = S5PV310_PA_SROM_BANK(1),
.end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
.start = EXYNOS4_PA_SROM_BANK(1),
.end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -154,16 +154,16 @@ static struct platform_device *smdkc210_devices[] __initdata = {
&s3c_device_i2c1,
&s3c_device_rtc,
&s3c_device_wdt,
&s5pv310_device_ac97,
&s5pv310_device_i2s0,
&s5pv310_device_pd[PD_MFC],
&s5pv310_device_pd[PD_G3D],
&s5pv310_device_pd[PD_LCD0],
&s5pv310_device_pd[PD_LCD1],
&s5pv310_device_pd[PD_CAM],
&s5pv310_device_pd[PD_TV],
&s5pv310_device_pd[PD_GPS],
&s5pv310_device_sysmmu,
&exynos4_device_ac97,
&exynos4_device_i2s0,
&exynos4_device_pd[PD_MFC],
&exynos4_device_pd[PD_G3D],
&exynos4_device_pd[PD_LCD0],
&exynos4_device_pd[PD_LCD1],
&exynos4_device_pd[PD_CAM],
&exynos4_device_pd[PD_TV],
&exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&smdkc210_smsc911x,
};
@ -216,8 +216,8 @@ static void __init smdkc210_machine_init(void)
MACHINE_START(SMDKC210, "SMDKC210")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = s5pv310_init_irq,
.init_irq = exynos4_init_irq,
.map_io = smdkc210_map_io,
.init_machine = smdkc210_machine_init,
.timer = &s5pv310_timer,
.timer = &exynos4_timer,
MACHINE_END

48
arch/arm/mach-s5pv310/mach-smdkv310.c → arch/arm/mach-exynos4/mach-smdkv310.c
View File

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5pv310/mach-smdkv310.c
/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -21,7 +21,7 @@
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
#include <plat/s5pv310.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
@ -77,10 +77,10 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = S5PV310_GPK0(2),
.ext_cd_gpio = EXYNOS4_GPK0(2),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
#endif
@ -88,17 +88,17 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = S5PV310_GPK0(2),
.ext_cd_gpio = EXYNOS4_GPK0(2),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = S5PV310_GPK2(2),
.ext_cd_gpio = EXYNOS4_GPK2(2),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
.max_width = 8,
.host_caps = MMC_CAP_8_BIT_DATA,
#endif
@ -106,15 +106,15 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
.cd_type = S3C_SDHCI_CD_GPIO,
.ext_cd_gpio = S5PV310_GPK2(2),
.ext_cd_gpio = EXYNOS4_GPK2(2),
.ext_cd_gpio_invert = 1,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct resource smdkv310_smsc911x_resources[] = {
[0] = {
.start = S5PV310_PA_SROM_BANK(1),
.end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
.start = EXYNOS4_PA_SROM_BANK(1),
.end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -154,16 +154,16 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&s3c_device_i2c1,
&s3c_device_rtc,
&s3c_device_wdt,
&s5pv310_device_ac97,
&s5pv310_device_i2s0,
&s5pv310_device_pd[PD_MFC],
&s5pv310_device_pd[PD_G3D],
&s5pv310_device_pd[PD_LCD0],
&s5pv310_device_pd[PD_LCD1],
&s5pv310_device_pd[PD_CAM],
&s5pv310_device_pd[PD_TV],
&s5pv310_device_pd[PD_GPS],
&s5pv310_device_sysmmu,
&exynos4_device_ac97,
&exynos4_device_i2s0,
&exynos4_device_pd[PD_MFC],
&exynos4_device_pd[PD_G3D],
&exynos4_device_pd[PD_LCD0],
&exynos4_device_pd[PD_LCD1],
&exynos4_device_pd[PD_CAM],
&exynos4_device_pd[PD_TV],
&exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu,
&samsung_asoc_dma,
&smdkv310_smsc911x,
};
@ -217,8 +217,8 @@ MACHINE_START(SMDKV310, "SMDKV310")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = s5pv310_init_irq,
.init_irq = exynos4_init_irq,
.map_io = smdkv310_map_io,
.init_machine = smdkv310_machine_init,
.timer = &s5pv310_timer,
.timer = &exynos4_timer,
MACHINE_END

650
arch/arm/mach-exynos4/mach-universal_c210.c Normal file
View File

@ -0,0 +1,650 @@
/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <linux/mfd/max8998.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/max8952.h>
#include <linux/mmc/host.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/iic.h>
#include <plat/sdhci.h>
#include <mach/map.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG256 | \
S5PV210_UFCON_RXTRIG256)
static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.ucon = UNIVERSAL_UCON_DEFAULT,
.ulcon = UNIVERSAL_ULCON_DEFAULT,
.ufcon = UNIVERSAL_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.ucon = UNIVERSAL_UCON_DEFAULT,
.ulcon = UNIVERSAL_ULCON_DEFAULT,
.ufcon = UNIVERSAL_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.ucon = UNIVERSAL_UCON_DEFAULT,
.ulcon = UNIVERSAL_ULCON_DEFAULT,
.ufcon = UNIVERSAL_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.ucon = UNIVERSAL_UCON_DEFAULT,
.ulcon = UNIVERSAL_ULCON_DEFAULT,
.ufcon = UNIVERSAL_UFCON_DEFAULT,
},
};
static struct regulator_consumer_supply max8952_consumer =
REGULATOR_SUPPLY("vddarm", NULL);
static struct max8952_platform_data universal_max8952_pdata __initdata = {
.gpio_vid0 = EXYNOS4_GPX0(3),
.gpio_vid1 = EXYNOS4_GPX0(4),
.gpio_en = -1, /* Not controllable, set "Always High" */
.default_mode = 0, /* vid0 = 0, vid1 = 0 */
.dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
.sync_freq = 0, /* default: fastest */
.ramp_speed = 0, /* default: fastest */
.reg_data = {
.constraints = {
.name = "VARM_1.2V",
.min_uV = 770000,
.max_uV = 1400000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
},
.num_consumer_supplies = 1,
.consumer_supplies = &max8952_consumer,
},
};
static struct regulator_consumer_supply lp3974_buck1_consumer =
REGULATOR_SUPPLY("vddint", NULL);
static struct regulator_consumer_supply lp3974_buck2_consumer =
REGULATOR_SUPPLY("vddg3d", NULL);
static struct regulator_init_data lp3974_buck1_data = {
.constraints = {
.name = "VINT_1.1V",
.min_uV = 750000,
.max_uV = 1500000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = 1,
.consumer_supplies = &lp3974_buck1_consumer,
};
static struct regulator_init_data lp3974_buck2_data = {
.constraints = {
.name = "VG3D_1.1V",
.min_uV = 750000,
.max_uV = 1500000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.state_mem = {
.disabled = 1,
},
},
.num_consumer_supplies = 1,
.consumer_supplies = &lp3974_buck2_consumer,
};
static struct regulator_init_data lp3974_buck3_data = {
.constraints = {
.name = "VCC_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data lp3974_buck4_data = {
.constraints = {
.name = "VMEM_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.apply_uV = 1,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo2_data = {
.constraints = {
.name = "VALIVE_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo3_data = {
.constraints = {
.name = "VUSB+MIPI_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo4_data = {
.constraints = {
.name = "VADC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo5_data = {
.constraints = {
.name = "VTF_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo6_data = {
.constraints = {
.name = "LDO6",
.min_uV = 2000000,
.max_uV = 2000000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo7_data = {
.constraints = {
.name = "VLCD+VMIPI_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo8_data = {
.constraints = {
.name = "VUSB+VDAC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo9_data = {
.constraints = {
.name = "VCC_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo10_data = {
.constraints = {
.name = "VPLL_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.boot_on = 1,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo11_data = {
.constraints = {
.name = "CAM_AF_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo12_data = {
.constraints = {
.name = "PS_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo13_data = {
.constraints = {
.name = "VHIC_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo14_data = {
.constraints = {
.name = "CAM_I_HOST_1.8V",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo15_data = {
.constraints = {
.name = "CAM_S_DIG+FM33_CORE_1.2V",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo16_data = {
.constraints = {
.name = "CAM_S_ANA_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_ldo17_data = {
.constraints = {
.name = "VCC_3.0V_LCD",
.min_uV = 3000000,
.max_uV = 3000000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_32khz_ap_data = {
.constraints = {
.name = "32KHz AP",
.always_on = 1,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data lp3974_32khz_cp_data = {
.constraints = {
.name = "32KHz CP",
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_vichg_data = {
.constraints = {
.name = "VICHG",
.state_mem = {
.disabled = 1,
},
},
};
static struct regulator_init_data lp3974_esafeout1_data = {
.constraints = {
.name = "SAFEOUT1",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.enabled = 1,
},
},
};
static struct regulator_init_data lp3974_esafeout2_data = {
.constraints = {
.name = "SAFEOUT2",
.boot_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.enabled = 1,
},
},
};
static struct max8998_regulator_data lp3974_regulators[] = {
{ MAX8998_LDO2, &lp3974_ldo2_data },
{ MAX8998_LDO3, &lp3974_ldo3_data },
{ MAX8998_LDO4, &lp3974_ldo4_data },
{ MAX8998_LDO5, &lp3974_ldo5_data },
{ MAX8998_LDO6, &lp3974_ldo6_data },
{ MAX8998_LDO7, &lp3974_ldo7_data },
{ MAX8998_LDO8, &lp3974_ldo8_data },
{ MAX8998_LDO9, &lp3974_ldo9_data },
{ MAX8998_LDO10, &lp3974_ldo10_data },
{ MAX8998_LDO11, &lp3974_ldo11_data },
{ MAX8998_LDO12, &lp3974_ldo12_data },
{ MAX8998_LDO13, &lp3974_ldo13_data },
{ MAX8998_LDO14, &lp3974_ldo14_data },
{ MAX8998_LDO15, &lp3974_ldo15_data },
{ MAX8998_LDO16, &lp3974_ldo16_data },
{ MAX8998_LDO17, &lp3974_ldo17_data },
{ MAX8998_BUCK1, &lp3974_buck1_data },
{ MAX8998_BUCK2, &lp3974_buck2_data },
{ MAX8998_BUCK3, &lp3974_buck3_data },
{ MAX8998_BUCK4, &lp3974_buck4_data },
{ MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
{ MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
{ MAX8998_ENVICHG, &lp3974_vichg_data },
{ MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
{ MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
};
static struct max8998_platform_data universal_lp3974_pdata = {
.num_regulators = ARRAY_SIZE(lp3974_regulators),
.regulators = lp3974_regulators,
.buck1_voltage1 = 1100000, /* INT */
.buck1_voltage2 = 1000000,
.buck1_voltage3 = 1100000,
.buck1_voltage4 = 1000000,
.buck1_set1 = EXYNOS4_GPX0(5),
.buck1_set2 = EXYNOS4_GPX0(6),
.buck2_voltage1 = 1200000, /* G3D */
.buck2_voltage2 = 1100000,
.buck1_default_idx = 0,
.buck2_set3 = EXYNOS4_GPE2(0),
.buck2_default_idx = 0,
.wakeup = true,
};
/* GPIO I2C 5 (PMIC) */
static struct i2c_board_info i2c5_devs[] __initdata = {
{
I2C_BOARD_INFO("max8952", 0xC0 >> 1),
.platform_data = &universal_max8952_pdata,
}, {
I2C_BOARD_INFO("lp3974", 0xCC >> 1),
.platform_data = &universal_lp3974_pdata,
},
};
/* GPIO KEYS */
static struct gpio_keys_button universal_gpio_keys_tables[] = {
{
.code = KEY_VOLUMEUP,
.gpio = EXYNOS4_GPX2(0), /* XEINT16 */
.desc = "gpio-keys: KEY_VOLUMEUP",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_VOLUMEDOWN,
.gpio = EXYNOS4_GPX2(1), /* XEINT17 */
.desc = "gpio-keys: KEY_VOLUMEDOWN",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_CONFIG,
.gpio = EXYNOS4_GPX2(2), /* XEINT18 */
.desc = "gpio-keys: KEY_CONFIG",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_CAMERA,
.gpio = EXYNOS4_GPX2(3), /* XEINT19 */
.desc = "gpio-keys: KEY_CAMERA",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_OK,
.gpio = EXYNOS4_GPX3(5), /* XEINT29 */
.desc = "gpio-keys: KEY_OK",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
},
};
static struct gpio_keys_platform_data universal_gpio_keys_data = {
.buttons = universal_gpio_keys_tables,
.nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
};
static struct platform_device universal_gpio_keys = {
.name = "gpio-keys",
.dev = {
.platform_data = &universal_gpio_keys_data,
},
};
/* eMMC */
static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE),
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply mmc0_supplies[] = {
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
};
static struct regulator_init_data mmc0_fixed_voltage_init_data = {
.constraints = {
.name = "VMEM_VDD_2.8V",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
.consumer_supplies = mmc0_supplies,
};
static struct fixed_voltage_config mmc0_fixed_voltage_config = {
.supply_name = "MASSMEMORY_EN",
.microvolts = 2800000,
.gpio = EXYNOS4_GPE1(3),
.enable_high = true,
.init_data = &mmc0_fixed_voltage_init_data,
};
static struct platform_device mmc0_fixed_voltage = {
.name = "reg-fixed-voltage",
.id = 0,
.dev = {
.platform_data = &mmc0_fixed_voltage_config,
},
};
/* SD */
static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE,
.ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
.ext_cd_gpio_invert = 1,
.cd_type = S3C_SDHCI_CD_GPIO,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* WiFi */
static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE,
.cd_type = S3C_SDHCI_CD_EXTERNAL,
};
static void __init universal_sdhci_init(void)
{
s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
}
/* I2C0 */
static struct i2c_board_info i2c0_devs[] __initdata = {
/* Camera, To be updated */
};
/* I2C1 */
static struct i2c_board_info i2c1_devs[] __initdata = {
/* Gyro, To be updated */
};
static struct platform_device *universal_devices[] __initdata = {
/* Samsung Platform Devices */
&mmc0_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
&s3c_device_i2c5,
/* Universal Devices */
&universal_gpio_keys,
&s5p_device_onenand,
};
static void __init universal_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
}
static void __init universal_machine_init(void)
{
universal_sdhci_init();
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
s3c_i2c5_set_platdata(NULL);
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
/* Last */
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
}
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = exynos4_init_irq,
.map_io = universal_map_io,
.init_machine = universal_machine_init,
.timer = &exynos4_timer,
MACHINE_END

421
arch/arm/mach-exynos4/mct.c Normal file
View File

@ -0,0 +1,421 @@
/* linux/arch/arm/mach-exynos4/mct.c
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 MCT(Multi-Core Timer) support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/percpu.h>
#include <mach/map.h>
#include <mach/regs-mct.h>
#include <asm/mach/time.h>
static unsigned long clk_cnt_per_tick;
static unsigned long clk_rate;
struct mct_clock_event_device {
struct clock_event_device *evt;
void __iomem *base;
};
struct mct_clock_event_device mct_tick[2];
static void exynos4_mct_write(unsigned int value, void *addr)
{
void __iomem *stat_addr;
u32 mask;
u32 i;
__raw_writel(value, addr);
switch ((u32) addr) {
case (u32) EXYNOS4_MCT_G_TCON:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 16; /* G_TCON write status */
break;
case (u32) EXYNOS4_MCT_G_COMP0_L:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 0; /* G_COMP0_L write status */
break;
case (u32) EXYNOS4_MCT_G_COMP0_U:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 1; /* G_COMP0_U write status */
break;
case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
break;
case (u32) EXYNOS4_MCT_G_CNT_L:
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
mask = 1 << 0; /* G_CNT_L write status */
break;
case (u32) EXYNOS4_MCT_G_CNT_U:
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
mask = 1 << 1; /* G_CNT_U write status */
break;
case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
mask = 1 << 3; /* L0_TCON write status */
break;
case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
mask = 1 << 3; /* L1_TCON write status */
break;
case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
mask = 1 << 0; /* L0_TCNTB write status */
break;
case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
mask = 1 << 0; /* L1_TCNTB write status */
break;
case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
mask = 1 << 1; /* L0_ICNTB write status */
break;
case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
mask = 1 << 1; /* L1_ICNTB write status */
break;
default:
return;
}
/* Wait maximum 1 ms until written values are applied */
for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
if (__raw_readl(stat_addr) & mask) {
__raw_writel(mask, stat_addr);
return;
}
panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
}
/* Clocksource handling */
static void exynos4_mct_frc_start(u32 hi, u32 lo)
{
u32 reg;
exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
reg = __raw_readl(EXYNOS4_MCT_G_TCON);
reg |= MCT_G_TCON_START;
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}
static cycle_t exynos4_frc_read(struct clocksource *cs)
{
unsigned int lo, hi;
u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
do {
hi = hi2;
lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
} while (hi != hi2);
return ((cycle_t)hi << 32) | lo;
}
struct clocksource mct_frc = {
.name = "mct-frc",
.rating = 400,
.read = exynos4_frc_read,
.mask = CLOCKSOURCE_MASK(64),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start(0, 0);
if (clocksource_register_hz(&mct_frc, clk_rate))
panic("%s: can't register clocksource\n", mct_frc.name);
}
static void exynos4_mct_comp0_stop(void)
{
unsigned int tcon;
tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
}
static void exynos4_mct_comp0_start(enum clock_event_mode mode,
unsigned long cycles)
{
unsigned int tcon;
cycle_t comp_cycle;
tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
if (mode == CLOCK_EVT_MODE_PERIODIC) {
tcon |= MCT_G_TCON_COMP0_AUTO_INC;
exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
}
comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
tcon |= MCT_G_TCON_COMP0_ENABLE;
exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
}
static int exynos4_comp_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
exynos4_mct_comp0_start(evt->mode, cycles);
return 0;
}
static void exynos4_comp_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
exynos4_mct_comp0_stop();
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static struct clock_event_device mct_comp_device = {
.name = "mct-comp",
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 250,
.set_next_event = exynos4_comp_set_next_event,
.set_mode = exynos4_comp_set_mode,
};
static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction mct_comp_event_irq = {
.name = "mct_comp_irq",
.flags = IRQF_TIMER | IRQF_IRQPOLL,
.handler = exynos4_mct_comp_isr,
.dev_id = &mct_comp_device,
};
static void exynos4_clockevent_init(void)
{
clk_cnt_per_tick = clk_rate / 2 / HZ;
clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
mct_comp_device.max_delta_ns =
clockevent_delta2ns(0xffffffff, &mct_comp_device);
mct_comp_device.min_delta_ns =
clockevent_delta2ns(0xf, &mct_comp_device);
mct_comp_device.cpumask = cpumask_of(0);
clockevents_register_device(&mct_comp_device);
setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
}
#ifdef CONFIG_LOCAL_TIMERS
/* Clock event handling */
static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
unsigned long tmp;
unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
tmp = __raw_readl(addr);
if (tmp & mask) {
tmp &= ~mask;
exynos4_mct_write(tmp, addr);
}
}
static void exynos4_mct_tick_start(unsigned long cycles,
struct mct_clock_event_device *mevt)
{
unsigned long tmp;
exynos4_mct_tick_stop(mevt);
tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
/* update interrupt count buffer */
exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
/* enable MCT tick interupt */
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
MCT_L_TCON_INTERVAL_MODE;
exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
}
static int exynos4_tick_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
exynos4_mct_tick_start(cycles, mevt);
return 0;
}
static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
exynos4_mct_tick_stop(mevt);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
break;
case CLOCK_EVT_MODE_ONESHOT:
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
case CLOCK_EVT_MODE_RESUME:
break;
}
}
static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
{
struct mct_clock_event_device *mevt = dev_id;
struct clock_event_device *evt = mevt->evt;
/*
* This is for supporting oneshot mode.
* Mct would generate interrupt periodically
* without explicit stopping.
*/
if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
exynos4_mct_tick_stop(mevt);
/* Clear the MCT tick interrupt */
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction mct_tick0_event_irq = {
.name = "mct_tick0_irq",
.flags = IRQF_TIMER | IRQF_NOBALANCING,
.handler = exynos4_mct_tick_isr,
};
static struct irqaction mct_tick1_event_irq = {
.name = "mct_tick1_irq",
.flags = IRQF_TIMER | IRQF_NOBALANCING,
.handler = exynos4_mct_tick_isr,
};
static void exynos4_mct_tick_init(struct clock_event_device *evt)
{
unsigned int cpu = smp_processor_id();
mct_tick[cpu].evt = evt;
if (cpu == 0) {
mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
evt->name = "mct_tick0";
} else {
mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
evt->name = "mct_tick1";
}
evt->cpumask = cpumask_of(cpu);
evt->set_next_event = exynos4_tick_set_next_event;
evt->set_mode = exynos4_tick_set_mode;
evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
evt->rating = 450;
clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
evt->max_delta_ns =
clockevent_delta2ns(0x7fffffff, evt);
evt->min_delta_ns =
clockevent_delta2ns(0xf, evt);
clockevents_register_device(evt);
exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
if (cpu == 0) {
mct_tick0_event_irq.dev_id = &mct_tick[cpu];
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
} else {
mct_tick1_event_irq.dev_id = &mct_tick[cpu];
irq_set_affinity(IRQ_MCT1, cpumask_of(1));
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
}
}
/* Setup the local clock events for a CPU */
void __cpuinit local_timer_setup(struct clock_event_device *evt)
{
exynos4_mct_tick_init(evt);
}
int local_timer_ack(void)
{
return 0;
}
#endif /* CONFIG_LOCAL_TIMERS */
static void __init exynos4_timer_resources(void)
{
struct clk *mct_clk;
mct_clk = clk_get(NULL, "xtal");
clk_rate = clk_get_rate(mct_clk);
}
static void __init exynos4_timer_init(void)
{
exynos4_timer_resources();
exynos4_clocksource_init();
exynos4_clockevent_init();
}
struct sys_timer exynos4_timer = {
.init = exynos4_timer_init,
};

12
arch/arm/mach-s5pv310/platsmp.c → arch/arm/mach-exynos4/platsmp.c
View File

@ -1,7 +1,7 @@
/* linux/arch/arm/mach-s5pv310/platsmp.c
/* linux/arch/arm/mach-exynos4/platsmp.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
*
@ -28,7 +28,7 @@
#include <mach/hardware.h>
#include <mach/regs-clock.h>
extern void s5pv310_secondary_startup(void);
extern void exynos4_secondary_startup(void);
/*
* control for which core is the next to come out of the secondary
@ -139,7 +139,7 @@ void __init smp_init_cpus(void)
/* sanity check */
if (ncores > NR_CPUS) {
printk(KERN_WARNING
"S5PV310: no. of cores (%d) greater than configured "
"EXYNOS4: no. of cores (%d) greater than configured "
"maximum of %d - clipping\n",
ncores, NR_CPUS);
ncores = NR_CPUS;
@ -168,5 +168,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
}

4
arch/arm/mach-s5pv310/setup-i2c0.c → arch/arm/mach-exynos4/setup-i2c0.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-s5pv310/setup-i2c0.c
* linux/arch/arm/mach-exynos4/setup-i2c0.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
@ -21,6 +21,6 @@ struct platform_device; /* don't need the contents */
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2,
s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}

4
arch/arm/mach-s5pv310/setup-i2c1.c → arch/arm/mach-exynos4/setup-i2c1.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-s5pv310/setup-i2c1.c
* linux/arch/arm/mach-exynos4/setup-i2c1.c
*
* Copyright (C) 2010 Samsung Electronics Co., Ltd.
*
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2,
s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}

4
arch/arm/mach-s5pv310/setup-i2c2.c → arch/arm/mach-exynos4/setup-i2c2.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-s5pv310/setup-i2c2.c
* linux/arch/arm/mach-exynos4/setup-i2c2.c
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
*
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
void s3c_i2c2_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2,
s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
}

4
arch/arm/mach-s5pv310/setup-i2c3.c → arch/arm/mach-exynos4/setup-i2c3.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-s5pv310/setup-i2c3.c
* linux/arch/arm/mach-exynos4/setup-i2c3.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
*
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
void s3c_i2c3_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2,
s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
}

4
arch/arm/mach-s5pv310/setup-i2c4.c → arch/arm/mach-exynos4/setup-i2c4.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-s5pv310/setup-i2c4.c
* linux/arch/arm/mach-exynos4/setup-i2c4.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
*
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
void s3c_i2c4_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV310_GPB(2), 2,
s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
}

4
arch/arm/mach-s5pv310/setup-i2c5.c → arch/arm/mach-exynos4/setup-i2c5.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-s5pv310/setup-i2c5.c
* linux/arch/arm/mach-exynos4/setup-i2c5.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
*
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
void s3c_i2c5_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV310_GPB(6), 2,
s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
}

4
arch/arm/mach-s5pv310/setup-i2c6.c → arch/arm/mach-exynos4/setup-i2c6.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-s5pv310/setup-i2c6.c
* linux/arch/arm/mach-exynos4/setup-i2c6.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
*
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
void s3c_i2c6_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2,
s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
}

4
arch/arm/mach-s5pv310/setup-i2c7.c → arch/arm/mach-exynos4/setup-i2c7.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-s5pv310/setup-i2c7.c
* linux/arch/arm/mach-exynos4/setup-i2c7.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
*
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
void s3c_i2c7_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2,
s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
}

52
arch/arm/mach-s5pv310/setup-sdhci-gpio.c → arch/arm/mach-exynos4/setup-sdhci-gpio.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
* EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -23,13 +23,13 @@
#include <plat/regs-sdhci.h>
#include <plat/sdhci.h>
void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
unsigned int gpio;
/* Set all the necessary GPK0[0:1] pins to special-function 2 */
for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
@ -37,14 +37,14 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
switch (width) {
case 8:
for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
/* Data pin GPK1[3:6] to special-funtion 3 */
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
}
case 4:
for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
/* Data pin GPK0[3:6] to special-funtion 2 */
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@ -55,25 +55,25 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
}
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
}
}
void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
unsigned int gpio;
/* Set all the necessary GPK1[0:1] pins to special-function 2 */
for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
}
for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
/* Data pin GPK1[3:6] to special-function 2 */
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@ -81,19 +81,19 @@ void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
}
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
}
}
void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
unsigned int gpio;
/* Set all the necessary GPK2[0:1] pins to special-function 2 */
for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
@ -101,14 +101,14 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
switch (width) {
case 8:
for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
/* Data pin GPK3[3:6] to special-function 3 */
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
}
case 4:
for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
/* Data pin GPK2[3:6] to special-function 2 */
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@ -119,25 +119,25 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
}
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
}
}
void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
{
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
unsigned int gpio;
/* Set all the necessary GPK3[0:1] pins to special-function 2 */
for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
}
for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
/* Data pin GPK3[3:6] to special-function 2 */
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@ -145,8 +145,8 @@ void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
}
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
}
}

12
arch/arm/mach-s5pv310/setup-sdhci.c → arch/arm/mach-exynos4/setup-sdhci.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
/* linux/arch/arm/mach-exynos4/setup-sdhci.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
* EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -23,14 +23,14 @@
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
char *s5pv310_hsmmc_clksrcs[4] = {
char *exynos4_hsmmc_clksrcs[4] = {
[0] = NULL,
[1] = NULL,
[2] = "sclk_mmc", /* mmc_bus */
[3] = NULL,
};
void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
struct mmc_ios *ios, struct mmc_card *card)
{
u32 ctrl2, ctrl3;

64
arch/arm/mach-s5pv310/time.c → arch/arm/mach-exynos4/time.c
View File

@ -1,9 +1,9 @@
/* linux/arch/arm/mach-s5pv310/time.c
/* linux/arch/arm/mach-exynos4/time.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 (and compatible) HRT support
* EXYNOS4 (and compatible) HRT support
* PWM 2/4 is used for this feature
*
* This program is free software; you can redistribute it and/or modify
@ -33,7 +33,7 @@ static struct clk *tdiv2;
static struct clk *tdiv4;
static struct clk *timerclk;
static void s5pv310_pwm_stop(unsigned int pwm_id)
static void exynos4_pwm_stop(unsigned int pwm_id)
{
unsigned long tcon;
@ -52,7 +52,7 @@ static void s5pv310_pwm_stop(unsigned int pwm_id)
__raw_writel(tcon, S3C2410_TCON);
}
static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
{
unsigned long tcon;
@ -86,7 +86,7 @@ static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
}
}
static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
{
unsigned long tcon;
@ -117,23 +117,23 @@ static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
__raw_writel(tcon, S3C2410_TCON);
}
static int s5pv310_pwm_set_next_event(unsigned long cycles,
static int exynos4_pwm_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
s5pv310_pwm_init(2, cycles);
s5pv310_pwm_start(2, 0);
exynos4_pwm_init(2, cycles);
exynos4_pwm_start(2, 0);
return 0;
}
static void s5pv310_pwm_set_mode(enum clock_event_mode mode,
static void exynos4_pwm_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
s5pv310_pwm_stop(2);
exynos4_pwm_stop(2);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
s5pv310_pwm_init(2, clock_count_per_tick);
s5pv310_pwm_start(2, 1);
exynos4_pwm_init(2, clock_count_per_tick);
exynos4_pwm_start(2, 1);
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
@ -149,11 +149,11 @@ static struct clock_event_device pwm_event_device = {
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.shift = 32,
.set_next_event = s5pv310_pwm_set_next_event,
.set_mode = s5pv310_pwm_set_mode,
.set_next_event = exynos4_pwm_set_next_event,
.set_mode = exynos4_pwm_set_mode,
};
irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
{
struct clock_event_device *evt = &pwm_event_device;
@ -162,13 +162,13 @@ irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
return IRQ_HANDLED;
}
static struct irqaction s5pv310_clock_event_irq = {
static struct irqaction exynos4_clock_event_irq = {
.name = "pwm_timer2_irq",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = s5pv310_clock_event_isr,
.handler = exynos4_clock_event_isr,
};
static void __init s5pv310_clockevent_init(void)
static void __init exynos4_clockevent_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
@ -198,10 +198,10 @@ static void __init s5pv310_clockevent_init(void)
pwm_event_device.cpumask = cpumask_of(0);
clockevents_register_device(&pwm_event_device);
setup_irq(IRQ_TIMER2, &s5pv310_clock_event_irq);
setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
}
static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
static cycle_t exynos4_pwm4_read(struct clocksource *cs)
{
return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
}
@ -209,12 +209,12 @@ static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
struct clocksource pwm_clocksource = {
.name = "pwm_timer4",
.rating = 250,
.read = s5pv310_pwm4_read,
.read = exynos4_pwm4_read,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS ,
};
static void __init s5pv310_clocksource_init(void)
static void __init exynos4_clocksource_init(void)
{
unsigned long pclk;
unsigned long clock_rate;
@ -226,14 +226,14 @@ static void __init s5pv310_clocksource_init(void)
clock_rate = clk_get_rate(tin4);
s5pv310_pwm_init(4, ~0);
s5pv310_pwm_start(4, 1);
exynos4_pwm_init(4, ~0);
exynos4_pwm_start(4, 1);
if (clocksource_register_hz(&pwm_clocksource, clock_rate))
panic("%s: can't register clocksource\n", pwm_clocksource.name);
}
static void __init s5pv310_timer_resources(void)
static void __init exynos4_timer_resources(void)
{
struct platform_device tmpdev;
@ -267,17 +267,17 @@ static void __init s5pv310_timer_resources(void)
clk_enable(tin4);
}
static void __init s5pv310_timer_init(void)
static void __init exynos4_timer_init(void)
{
#ifdef CONFIG_LOCAL_TIMERS
twd_base = S5P_VA_TWD;
#endif
s5pv310_timer_resources();
s5pv310_clockevent_init();
s5pv310_clocksource_init();
exynos4_timer_resources();
exynos4_clockevent_init();
exynos4_clocksource_init();
}
struct sys_timer s5pv310_timer = {
.init = s5pv310_timer_init,
struct sys_timer exynos4_timer = {
.init = exynos4_timer_init,
};

151
arch/arm/mach-s5pv310/Kconfig
View File

@ -1,151 +0,0 @@
# arch/arm/mach-s5pv310/Kconfig
#
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
# Configuration options for the S5PV310
if ARCH_S5PV310
config CPU_S5PV310
bool
select S3C_PL330_DMA
help
Enable S5PV310 CPU support
config S5PV310_DEV_PD
bool
help
Compile in platform device definitions for Power Domain
config S5PV310_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config S5PV310_SETUP_I2C2
bool
help
Common setup code for i2c bus 2.
config S5PV310_SETUP_I2C3
bool
help
Common setup code for i2c bus 3.
config S5PV310_SETUP_I2C4
bool
help
Common setup code for i2c bus 4.
config S5PV310_SETUP_I2C5
bool
help
Common setup code for i2c bus 5.
config S5PV310_SETUP_I2C6
bool
help
Common setup code for i2c bus 6.
config S5PV310_SETUP_I2C7
bool
help
Common setup code for i2c bus 7.
config S5PV310_SETUP_SDHCI
bool
select S5PV310_SETUP_SDHCI_GPIO
help
Internal helper functions for S5PV310 based SDHCI systems.
config S5PV310_SETUP_SDHCI_GPIO
bool
help
Common setup code for SDHCI gpio.
config S5PV310_DEV_SYSMMU
bool
help
Common setup code for SYSTEM MMU in S5PV310
# machine support
menu "S5PC210 Machines"
config MACH_SMDKC210
bool "SMDKC210"
select CPU_S5PV310
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S5PV310_DEV_PD
select S5PV310_SETUP_I2C1
select S5PV310_SETUP_SDHCI
select S5PV310_DEV_SYSMMU
help
Machine support for Samsung SMDKC210
S5PC210(MCP) is one of package option of S5PV310
config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board"
select CPU_S5PV310
select S5P_DEV_ONENAND
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S5PV310_SETUP_SDHCI
select S3C_DEV_I2C1
select S5PV310_SETUP_I2C1
help
Machine support for Samsung Mobile Universal S5PC210 Reference
Board. S5PC210(MCP) is one of package option of S5PV310
endmenu
menu "S5PV310 Machines"
config MACH_SMDKV310
bool "SMDKV310"
select CPU_S5PV310
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S5PV310_DEV_PD
select S5PV310_DEV_SYSMMU
select S5PV310_SETUP_I2C1
select S5PV310_SETUP_SDHCI
help
Machine support for Samsung SMDKV310
endmenu
comment "Configuration for HSMMC bus width"
menu "Use 8-bit bus width"
config S5PV310_SDHCI_CH0_8BIT
bool "Channel 0 with 8-bit bus"
help
Support HSMMC Channel 0 8-bit bus.
If selected, Channel 1 is disabled.
config S5PV310_SDHCI_CH2_8BIT
bool "Channel 2 with 8-bit bus"
help
Support HSMMC Channel 2 8-bit bus.
If selected, Channel 3 is disabled.
endmenu
endif

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arch/arm/mach-s5pv310/Makefile
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# arch/arm/mach-s5pv310/Makefile
#
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
#
# Licensed under GPLv2
obj-y :=
obj-m :=
obj-n :=
obj- :=
# Core support for S5PV310 system
obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
# machine support
obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
# device support
obj-y += dev-audio.o
obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o
obj-$(CONFIG_S5PV310_DEV_SYSMMU) += dev-sysmmu.o
obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
obj-$(CONFIG_S5PV310_SETUP_I2C4) += setup-i2c4.o
obj-$(CONFIG_S5PV310_SETUP_I2C5) += setup-i2c5.o
obj-$(CONFIG_S5PV310_SETUP_I2C6) += setup-i2c6.o
obj-$(CONFIG_S5PV310_SETUP_I2C7) += setup-i2c7.o
obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o

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arch/arm/mach-s5pv310/include/mach/gpio.h
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/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV310 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
#define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq
/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
/* GPIO bank sizes */
#define S5PV310_GPIO_A0_NR (8)
#define S5PV310_GPIO_A1_NR (6)
#define S5PV310_GPIO_B_NR (8)
#define S5PV310_GPIO_C0_NR (5)
#define S5PV310_GPIO_C1_NR (5)
#define S5PV310_GPIO_D0_NR (4)
#define S5PV310_GPIO_D1_NR (4)
#define S5PV310_GPIO_E0_NR (5)
#define S5PV310_GPIO_E1_NR (8)
#define S5PV310_GPIO_E2_NR (6)
#define S5PV310_GPIO_E3_NR (8)
#define S5PV310_GPIO_E4_NR (8)
#define S5PV310_GPIO_F0_NR (8)
#define S5PV310_GPIO_F1_NR (8)
#define S5PV310_GPIO_F2_NR (8)
#define S5PV310_GPIO_F3_NR (6)
#define S5PV310_GPIO_J0_NR (8)
#define S5PV310_GPIO_J1_NR (5)
#define S5PV310_GPIO_K0_NR (7)
#define S5PV310_GPIO_K1_NR (7)
#define S5PV310_GPIO_K2_NR (7)
#define S5PV310_GPIO_K3_NR (7)
#define S5PV310_GPIO_L0_NR (8)
#define S5PV310_GPIO_L1_NR (3)
#define S5PV310_GPIO_L2_NR (8)
#define S5PV310_GPIO_X0_NR (8)
#define S5PV310_GPIO_X1_NR (8)
#define S5PV310_GPIO_X2_NR (8)
#define S5PV310_GPIO_X3_NR (8)
#define S5PV310_GPIO_Z_NR (7)
/* GPIO bank numbers */
#define S5PV310_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s5p_gpio_number {
S5PV310_GPIO_A0_START = 0,
S5PV310_GPIO_A1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A0),
S5PV310_GPIO_B_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A1),
S5PV310_GPIO_C0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_B),
S5PV310_GPIO_C1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C0),
S5PV310_GPIO_D0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C1),
S5PV310_GPIO_D1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D0),
S5PV310_GPIO_E0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D1),
S5PV310_GPIO_E1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E0),
S5PV310_GPIO_E2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E1),
S5PV310_GPIO_E3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E2),
S5PV310_GPIO_E4_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E3),
S5PV310_GPIO_F0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E4),
S5PV310_GPIO_F1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F0),
S5PV310_GPIO_F2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F1),
S5PV310_GPIO_F3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F2),
S5PV310_GPIO_J0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F3),
S5PV310_GPIO_J1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J0),
S5PV310_GPIO_K0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J1),
S5PV310_GPIO_K1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K0),
S5PV310_GPIO_K2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K1),
S5PV310_GPIO_K3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K2),
S5PV310_GPIO_L0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K3),
S5PV310_GPIO_L1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L0),
S5PV310_GPIO_L2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L1),
S5PV310_GPIO_X0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L2),
S5PV310_GPIO_X1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X0),
S5PV310_GPIO_X2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X1),
S5PV310_GPIO_X3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X2),
S5PV310_GPIO_Z_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X3),
};
/* S5PV310 GPIO number definitions */
#define S5PV310_GPA0(_nr) (S5PV310_GPIO_A0_START + (_nr))
#define S5PV310_GPA1(_nr) (S5PV310_GPIO_A1_START + (_nr))
#define S5PV310_GPB(_nr) (S5PV310_GPIO_B_START + (_nr))
#define S5PV310_GPC0(_nr) (S5PV310_GPIO_C0_START + (_nr))
#define S5PV310_GPC1(_nr) (S5PV310_GPIO_C1_START + (_nr))
#define S5PV310_GPD0(_nr) (S5PV310_GPIO_D0_START + (_nr))
#define S5PV310_GPD1(_nr) (S5PV310_GPIO_D1_START + (_nr))
#define S5PV310_GPE0(_nr) (S5PV310_GPIO_E0_START + (_nr))
#define S5PV310_GPE1(_nr) (S5PV310_GPIO_E1_START + (_nr))
#define S5PV310_GPE2(_nr) (S5PV310_GPIO_E2_START + (_nr))
#define S5PV310_GPE3(_nr) (S5PV310_GPIO_E3_START + (_nr))
#define S5PV310_GPE4(_nr) (S5PV310_GPIO_E4_START + (_nr))
#define S5PV310_GPF0(_nr) (S5PV310_GPIO_F0_START + (_nr))
#define S5PV310_GPF1(_nr) (S5PV310_GPIO_F1_START + (_nr))
#define S5PV310_GPF2(_nr) (S5PV310_GPIO_F2_START + (_nr))
#define S5PV310_GPF3(_nr) (S5PV310_GPIO_F3_START + (_nr))
#define S5PV310_GPJ0(_nr) (S5PV310_GPIO_J0_START + (_nr))
#define S5PV310_GPJ1(_nr) (S5PV310_GPIO_J1_START + (_nr))
#define S5PV310_GPK0(_nr) (S5PV310_GPIO_K0_START + (_nr))
#define S5PV310_GPK1(_nr) (S5PV310_GPIO_K1_START + (_nr))
#define S5PV310_GPK2(_nr) (S5PV310_GPIO_K2_START + (_nr))
#define S5PV310_GPK3(_nr) (S5PV310_GPIO_K3_START + (_nr))
#define S5PV310_GPL0(_nr) (S5PV310_GPIO_L0_START + (_nr))
#define S5PV310_GPL1(_nr) (S5PV310_GPIO_L1_START + (_nr))
#define S5PV310_GPL2(_nr) (S5PV310_GPIO_L2_START + (_nr))
#define S5PV310_GPX0(_nr) (S5PV310_GPIO_X0_START + (_nr))
#define S5PV310_GPX1(_nr) (S5PV310_GPIO_X1_START + (_nr))
#define S5PV310_GPX2(_nr) (S5PV310_GPIO_X2_START + (_nr))
#define S5PV310_GPX3(_nr) (S5PV310_GPIO_X3_START + (_nr))
#define S5PV310_GPZ(_nr) (S5PV310_GPIO_Z_START + (_nr))
/* the end of the S5PV310 specific gpios */
#define S5PV310_GPIO_END (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1)
#define S3C_GPIO_END S5PV310_GPIO_END
/* define the number of gpios we need to the one after the GPZ() range */
#define ARCH_NR_GPIOS (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */

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arch/arm/mach-s5pv310/include/mach/map.h
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/* linux/arch/arm/mach-s5pv310/include/mach/map.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV310 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
/*
* S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400.
* So need to define it, and here is to avoid redefinition warning.
*/
#define S3C_UART_OFFSET (0x10000)
#include <plat/map-s5p.h>
#define S5PV310_PA_SYSRAM 0x02025000
#define S5PV310_PA_I2S0 0x03830000
#define S5PV310_PA_I2S1 0xE3100000
#define S5PV310_PA_I2S2 0xE2A00000
#define S5PV310_PA_PCM0 0x03840000
#define S5PV310_PA_PCM1 0x13980000
#define S5PV310_PA_PCM2 0x13990000
#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
#define S5PC210_PA_ONENAND 0x0C000000
#define S5PC210_PA_ONENAND_DMA 0x0C600000
#define S5PV310_PA_CHIPID 0x10000000
#define S5PV310_PA_SYSCON 0x10010000
#define S5PV310_PA_PMU 0x10020000
#define S5PV310_PA_CMU 0x10030000
#define S5PV310_PA_WATCHDOG 0x10060000
#define S5PV310_PA_RTC 0x10070000
#define S5PV310_PA_DMC0 0x10400000
#define S5PV310_PA_COMBINER 0x10448000
#define S5PV310_PA_COREPERI 0x10500000
#define S5PV310_PA_GIC_CPU 0x10500100
#define S5PV310_PA_TWD 0x10500600
#define S5PV310_PA_GIC_DIST 0x10501000
#define S5PV310_PA_L2CC 0x10502000
#define S5PV310_PA_MDMA 0x10810000
#define S5PV310_PA_PDMA0 0x12680000
#define S5PV310_PA_PDMA1 0x12690000
#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
#define S5PV310_PA_SYSMMU_SSS 0x10A50000
#define S5PV310_PA_SYSMMU_FIMC0 0x11A20000
#define S5PV310_PA_SYSMMU_FIMC1 0x11A30000
#define S5PV310_PA_SYSMMU_FIMC2 0x11A40000
#define S5PV310_PA_SYSMMU_FIMC3 0x11A50000
#define S5PV310_PA_SYSMMU_JPEG 0x11A60000
#define S5PV310_PA_SYSMMU_FIMD0 0x11E20000
#define S5PV310_PA_SYSMMU_FIMD1 0x12220000
#define S5PV310_PA_SYSMMU_PCIe 0x12620000
#define S5PV310_PA_SYSMMU_G2D 0x12A20000
#define S5PV310_PA_SYSMMU_ROTATOR 0x12A30000
#define S5PV310_PA_SYSMMU_MDMA2 0x12A40000
#define S5PV310_PA_SYSMMU_TV 0x12E20000
#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
#define S5PV310_PA_GPIO1 0x11400000
#define S5PV310_PA_GPIO2 0x11000000
#define S5PV310_PA_GPIO3 0x03860000
#define S5PV310_PA_MIPI_CSIS0 0x11880000
#define S5PV310_PA_MIPI_CSIS1 0x11890000
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define S5PV310_PA_SROMC 0x12570000
#define S5PV310_PA_UART 0x13800000
#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define S5PV310_PA_AC97 0x139A0000
#define S5PV310_PA_TIMER 0x139D0000
#define S5PV310_PA_SDRAM 0x40000000
#define S5PV310_PA_SPDIF 0xE1100000
/* Compatibiltiy Defines */
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
#define S3C_PA_IIC S5PV310_PA_IIC(0)
#define S3C_PA_IIC1 S5PV310_PA_IIC(1)
#define S3C_PA_IIC2 S5PV310_PA_IIC(2)
#define S3C_PA_IIC3 S5PV310_PA_IIC(3)
#define S3C_PA_IIC4 S5PV310_PA_IIC(4)
#define S3C_PA_IIC5 S5PV310_PA_IIC(5)
#define S3C_PA_IIC6 S5PV310_PA_IIC(6)
#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
#define S3C_PA_RTC S5PV310_PA_RTC
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV310_PA_SDRAM
#define S5P_PA_SROMC S5PV310_PA_SROMC
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
#define S5P_PA_TIMER S5PV310_PA_TIMER
/* UART */
#define S3C_PA_UART S5PV310_PA_UART
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#define S5P_PA_UART4 S5P_PA_UART(4)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

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arch/arm/mach-s5pv310/include/mach/regs-gpio.h
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/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5PV310 - GPIO (including EINT) register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H __FILE__
#include <mach/map.h>
#include <mach/irqs.h>
#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00)
#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4))
#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4))
#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4))
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
#define EINT_MODE S3C_GPIO_SFN(0xf)
#define EINT_GPIO_0(x) S5PV310_GPX0(x)
#define EINT_GPIO_1(x) S5PV310_GPX1(x)
#define EINT_GPIO_2(x) S5PV310_GPX2(x)
#define EINT_GPIO_3(x) S5PV310_GPX3(x)
#endif /* __ASM_ARCH_REGS_GPIO_H */

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arch/arm/mach-s5pv310/mach-universal_c210.c
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/* linux/arch/arm/mach-s5pv310/mach-universal_c210.c
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/serial_core.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/mmc/host.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <plat/regs-serial.h>
#include <plat/s5pv310.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
#include <mach/map.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
S3C2410_UCON_TXIRQMODE | \
S3C2410_UCON_RXIRQMODE | \
S3C2410_UCON_RXFIFO_TOI | \
S3C2443_UCON_RXERR_IRQEN)
#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
S5PV210_UFCON_TXTRIG256 | \
S5PV210_UFCON_RXTRIG256)
static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
[0] = {
.hwport = 0,
.ucon = UNIVERSAL_UCON_DEFAULT,
.ulcon = UNIVERSAL_ULCON_DEFAULT,
.ufcon = UNIVERSAL_UFCON_DEFAULT,
},
[1] = {
.hwport = 1,
.ucon = UNIVERSAL_UCON_DEFAULT,
.ulcon = UNIVERSAL_ULCON_DEFAULT,
.ufcon = UNIVERSAL_UFCON_DEFAULT,
},
[2] = {
.hwport = 2,
.ucon = UNIVERSAL_UCON_DEFAULT,
.ulcon = UNIVERSAL_ULCON_DEFAULT,
.ufcon = UNIVERSAL_UFCON_DEFAULT,
},
[3] = {
.hwport = 3,
.ucon = UNIVERSAL_UCON_DEFAULT,
.ulcon = UNIVERSAL_ULCON_DEFAULT,
.ufcon = UNIVERSAL_UFCON_DEFAULT,
},
};
static struct gpio_keys_button universal_gpio_keys_tables[] = {
{
.code = KEY_VOLUMEUP,
.gpio = S5PV310_GPX2(0), /* XEINT16 */
.desc = "gpio-keys: KEY_VOLUMEUP",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_VOLUMEDOWN,
.gpio = S5PV310_GPX2(1), /* XEINT17 */
.desc = "gpio-keys: KEY_VOLUMEDOWN",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_CONFIG,
.gpio = S5PV310_GPX2(2), /* XEINT18 */
.desc = "gpio-keys: KEY_CONFIG",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_CAMERA,
.gpio = S5PV310_GPX2(3), /* XEINT19 */
.desc = "gpio-keys: KEY_CAMERA",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
}, {
.code = KEY_OK,
.gpio = S5PV310_GPX3(5), /* XEINT29 */
.desc = "gpio-keys: KEY_OK",
.type = EV_KEY,
.active_low = 1,
.debounce_interval = 1,
},
};
static struct gpio_keys_platform_data universal_gpio_keys_data = {
.buttons = universal_gpio_keys_tables,
.nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
};
static struct platform_device universal_gpio_keys = {
.name = "gpio-keys",
.dev = {
.platform_data = &universal_gpio_keys_data,
},
};
/* eMMC */
static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
.max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE),
.cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
static struct regulator_consumer_supply mmc0_supplies[] = {
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
};
static struct regulator_init_data mmc0_fixed_voltage_init_data = {
.constraints = {
.name = "VMEM_VDD_2.8V",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
.consumer_supplies = mmc0_supplies,
};
static struct fixed_voltage_config mmc0_fixed_voltage_config = {
.supply_name = "MASSMEMORY_EN",
.microvolts = 2800000,
.gpio = S5PV310_GPE1(3),
.enable_high = true,
.init_data = &mmc0_fixed_voltage_init_data,
};
static struct platform_device mmc0_fixed_voltage = {
.name = "reg-fixed-voltage",
.id = 0,
.dev = {
.platform_data = &mmc0_fixed_voltage_config,
},
};
/* SD */
static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE,
.ext_cd_gpio = S5PV310_GPX3(4), /* XEINT_28 */
.ext_cd_gpio_invert = 1,
.cd_type = S3C_SDHCI_CD_GPIO,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
/* WiFi */
static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
.max_width = 4,
.host_caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_DISABLE,
.cd_type = S3C_SDHCI_CD_EXTERNAL,
};
static void __init universal_sdhci_init(void)
{
s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
}
/* I2C0 */
static struct i2c_board_info i2c0_devs[] __initdata = {
/* Camera, To be updated */
};
/* I2C1 */
static struct i2c_board_info i2c1_devs[] __initdata = {
/* Gyro, To be updated */
};
static struct platform_device *universal_devices[] __initdata = {
/* Samsung Platform Devices */
&mmc0_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
/* Universal Devices */
&universal_gpio_keys,
&s5p_device_onenand,
};
static void __init universal_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
}
static void __init universal_machine_init(void)
{
universal_sdhci_init();
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
/* Last */
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
}
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
.boot_params = S5P_PA_SDRAM + 0x100,
.init_irq = s5pv310_init_irq,
.map_io = universal_map_io,
.init_machine = universal_machine_init,
.timer = &s5pv310_timer,
MACHINE_END

2
arch/arm/mm/Kconfig
View File

@ -812,7 +812,7 @@ config CACHE_L2X0
bool "Enable the L2x0 outer cache controller"
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
default y
select OUTER_CACHE

8
arch/arm/plat-s5p/Kconfig
View File

@ -7,10 +7,10 @@
config PLAT_S5P
bool
depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
default y
select ARM_VIC if !ARCH_S5PV310
select ARM_GIC if ARCH_S5PV310
select ARM_VIC if !ARCH_EXYNOS4
select ARM_GIC if ARCH_EXYNOS4
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select S3C_GPIO_TRACK
@ -41,7 +41,7 @@ comment "System MMU"
config S5P_SYSTEM_MMU
bool "S5P SYSTEM MMU"
depends on ARCH_S5PV310
depends on ARCH_EXYNOS4
help
Say Y here if you want to enable System MMU

25
arch/arm/plat-s5p/cpu.c
View File

@ -1,7 +1,7 @@
/* linux/arch/arm/plat-s5p/cpu.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P CPU Support
*
@ -12,17 +12,20 @@
#include <linux/init.h>
#include <linux/module.h>
#include <mach/map.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/s5p6440.h>
#include <plat/s5p6442.h>
#include <plat/s5p6450.h>
#include <plat/s5pc100.h>
#include <plat/s5pv210.h>
#include <plat/s5pv310.h>
#include <plat/exynos4.h>
/* table of supported CPUs */
@ -31,7 +34,7 @@ static const char name_s5p6442[] = "S5P6442";
static const char name_s5p6450[] = "S5P6450";
static const char name_s5pc100[] = "S5PC100";
static const char name_s5pv210[] = "S5PV210/S5PC110";
static const char name_s5pv310[] = "S5PV310";
static const char name_exynos4210[] = "EXYNOS4210";
static struct cpu_table cpu_ids[] __initdata = {
{
@ -75,13 +78,13 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = s5pv210_init,
.name = name_s5pv210,
}, {
.idcode = 0x43200000,
.idcode = 0x43210000,
.idmask = 0xfffff000,
.map_io = s5pv310_map_io,
.init_clocks = s5pv310_init_clocks,
.init_uarts = s5pv310_init_uarts,
.init = s5pv310_init,
.name = name_s5pv310,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos4_init,
.name = name_exynos4210,
},
};

34
arch/arm/plat-s5p/include/plat/exynos4.h Normal file
View File

@ -0,0 +1,34 @@
/* linux/arch/arm/plat-s5p/include/plat/exynos4.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for exynos4 cpu support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Common init code for EXYNOS4 related SoCs */
extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void exynos4_register_clocks(void);
extern void exynos4_setup_clocks(void);
#ifdef CONFIG_CPU_EXYNOS4210
extern int exynos4_init(void);
extern void exynos4_init_irq(void);
extern void exynos4_map_io(void);
extern void exynos4_init_clocks(int xtal);
extern struct sys_timer exynos4_timer;
#define exynos4_init_uarts exynos4_common_init_uarts
#else
#define exynos4_init_clocks NULL
#define exynos4_init_uarts NULL
#define exynos4_map_io NULL
#define exynos4_init NULL
#endif

34
arch/arm/plat-s5p/include/plat/s5pv310.h
View File

@ -1,34 +0,0 @@
/* linux/arch/arm/plat-s5p/include/plat/s5pv310.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Header file for s5pv310 cpu support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Common init code for S5PV310 related SoCs */
extern void s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
extern void s5pv310_register_clocks(void);
extern void s5pv310_setup_clocks(void);
#ifdef CONFIG_CPU_S5PV310
extern int s5pv310_init(void);
extern void s5pv310_init_irq(void);
extern void s5pv310_map_io(void);
extern void s5pv310_init_clocks(int xtal);
extern struct sys_timer s5pv310_timer;
#define s5pv310_init_uarts s5pv310_common_init_uarts
#else
#define s5pv310_init_clocks NULL
#define s5pv310_init_uarts NULL
#define s5pv310_map_io NULL
#define s5pv310_init NULL
#endif

23
arch/arm/plat-samsung/include/plat/devs.h
View File

@ -1,4 +1,7 @@
/* arch/arm/plat-samsung/include/plat/devs.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (c) 2004 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
@ -96,15 +99,15 @@ extern struct platform_device s5pv210_device_iis1;
extern struct platform_device s5pv210_device_iis2;
extern struct platform_device s5pv210_device_spdif;
extern struct platform_device s5pv310_device_ac97;
extern struct platform_device s5pv310_device_pcm0;
extern struct platform_device s5pv310_device_pcm1;
extern struct platform_device s5pv310_device_pcm2;
extern struct platform_device s5pv310_device_i2s0;
extern struct platform_device s5pv310_device_i2s1;
extern struct platform_device s5pv310_device_i2s2;
extern struct platform_device s5pv310_device_spdif;
extern struct platform_device s5pv310_device_pd[];
extern struct platform_device exynos4_device_ac97;
extern struct platform_device exynos4_device_pcm0;
extern struct platform_device exynos4_device_pcm1;
extern struct platform_device exynos4_device_pcm2;
extern struct platform_device exynos4_device_i2s0;
extern struct platform_device exynos4_device_i2s1;
extern struct platform_device exynos4_device_i2s2;
extern struct platform_device exynos4_device_spdif;
extern struct platform_device exynos4_device_pd[];
extern struct platform_device s5p6442_device_pcm0;
extern struct platform_device s5p6442_device_pcm1;
@ -137,7 +140,7 @@ extern struct platform_device s5p_device_fimc2;
extern struct platform_device s5p_device_mipi_csis0;
extern struct platform_device s5p_device_mipi_csis1;
extern struct platform_device s5pv310_device_sysmmu;
extern struct platform_device exynos4_device_sysmmu;
/* s3c2440 specific devices */

4
arch/arm/plat-samsung/include/plat/pd.h
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/plat-samsung/include/plat/pd.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
@ -17,7 +17,7 @@ struct samsung_pd_info {
void __iomem *base;
};
enum s5pv310_pd_block {
enum exynos4_pd_block {
PD_MFC,
PD_G3D,
PD_LCD0,

63
arch/arm/plat-samsung/include/plat/sdhci.h
View File

@ -1,4 +1,7 @@
/* linux/arch/arm/plat-s3c/include/plat/sdhci.h
/* linux/arch/arm/plat-samsung/include/plat/sdhci.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
@ -119,10 +122,10 @@ extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
extern void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
/* S3C2416 SDHCI setup */
@ -334,57 +337,57 @@ static inline void s5pv210_default_sdhci3(void) { }
#endif /* CONFIG_S5PV210_SETUP_SDHCI */
/* S5PV310 SDHCI setup */
#ifdef CONFIG_S5PV310_SETUP_SDHCI
extern char *s5pv310_hsmmc_clksrcs[4];
/* EXYNOS4 SDHCI setup */
#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
extern char *exynos4_hsmmc_clksrcs[4];
extern void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev,
extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev,
void __iomem *r,
struct mmc_ios *ios,
struct mmc_card *card);
static inline void s5pv310_default_sdhci0(void)
static inline void exynos4_default_sdhci0(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC
s3c_hsmmc0_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = s5pv310_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
#endif
}
static inline void s5pv310_default_sdhci1(void)
static inline void exynos4_default_sdhci1(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC1
s3c_hsmmc1_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = s5pv310_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
#endif
}
static inline void s5pv310_default_sdhci2(void)
static inline void exynos4_default_sdhci2(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC2
s3c_hsmmc2_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = s5pv310_setup_sdhci2_cfg_gpio;
s3c_hsmmc2_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
#endif
}
static inline void s5pv310_default_sdhci3(void)
static inline void exynos4_default_sdhci3(void)
{
#ifdef CONFIG_S3C_DEV_HSMMC3
s3c_hsmmc3_def_platdata.clocks = s5pv310_hsmmc_clksrcs;
s3c_hsmmc3_def_platdata.cfg_gpio = s5pv310_setup_sdhci3_cfg_gpio;
s3c_hsmmc3_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card;
s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
#endif
}
#else
static inline void s5pv310_default_sdhci0(void) { }
static inline void s5pv310_default_sdhci1(void) { }
static inline void s5pv310_default_sdhci2(void) { }
static inline void s5pv310_default_sdhci3(void) { }
static inline void exynos4_default_sdhci0(void) { }
static inline void exynos4_default_sdhci1(void) { }
static inline void exynos4_default_sdhci2(void) { }
static inline void exynos4_default_sdhci3(void) { }
#endif /* CONFIG_S5PV310_SETUP_SDHCI */
#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
#endif /* __PLAT_S3C_SDHCI_H */

2
drivers/mtd/onenand/Kconfig
View File

@ -32,7 +32,7 @@ config MTD_ONENAND_OMAP2
config MTD_ONENAND_SAMSUNG
tristate "OneNAND on Samsung SOC controller support"
depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310
depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4
help
Support for a OneNAND flash device connected to an Samsung SOC.
S3C64XX/S5PC100 use command mapping method.

4
drivers/tty/serial/Kconfig
View File

@ -537,8 +537,8 @@ config SERIAL_S3C6400
config SERIAL_S5PV210
tristate "Samsung S5PV210 Serial port support"
depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442 || CPU_S5PV310)
select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_S5PV310)
depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442 || CPU_EXYNOS4210)
select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_EXYNOS4210)
default y
help
Serial port support for Samsung's S5P Family of SoC's

2
sound/soc/samsung/Kconfig
View File

@ -1,6 +1,6 @@
config SND_SOC_SAMSUNG
tristate "ASoC support for Samsung"
depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PV310
depends on ARCH_S3C2410 || ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_EXYNOS4
select S3C64XX_DMA if ARCH_S3C64XX
select S3C2410_DMA if ARCH_S3C2410
help