reset: socfpga: fix for 64-bit compilation
The SoCFPGA Stratix10 reset controller has 32-bit registers. Thus, we cannot use BITS_PER_LONG in computing the register and bit offset. Instead, we should be using the width of the hardware register for the calculation. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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@ -40,8 +40,9 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
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struct socfpga_reset_data *data = container_of(rcdev,
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struct socfpga_reset_data,
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rcdev);
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int bank = id / BITS_PER_LONG;
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int offset = id % BITS_PER_LONG;
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int reg_width = sizeof(u32);
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int bank = id / (reg_width * BITS_PER_BYTE);
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int offset = id % (reg_width * BITS_PER_BYTE);
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unsigned long flags;
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u32 reg;
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@ -61,8 +62,9 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
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struct socfpga_reset_data,
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rcdev);
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int bank = id / BITS_PER_LONG;
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int offset = id % BITS_PER_LONG;
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int reg_width = sizeof(u32);
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int bank = id / (reg_width * BITS_PER_BYTE);
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int offset = id % (reg_width * BITS_PER_BYTE);
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unsigned long flags;
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u32 reg;
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@ -81,8 +83,9 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev,
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{
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struct socfpga_reset_data *data = container_of(rcdev,
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struct socfpga_reset_data, rcdev);
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int bank = id / BITS_PER_LONG;
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int offset = id % BITS_PER_LONG;
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int reg_width = sizeof(u32);
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int bank = id / (reg_width * BITS_PER_BYTE);
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int offset = id % (reg_width * BITS_PER_BYTE);
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u32 reg;
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reg = readl(data->membase + (bank * BANK_INCREMENT));
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@ -132,7 +135,7 @@ static int socfpga_reset_probe(struct platform_device *pdev)
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spin_lock_init(&data->lock);
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data->rcdev.owner = THIS_MODULE;
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data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
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data->rcdev.nr_resets = NR_BANKS * (sizeof(u32) * BITS_PER_BYTE);
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data->rcdev.ops = &socfpga_reset_ops;
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data->rcdev.of_node = pdev->dev.of_node;
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