Merge branch 'common/dma' into sh-latest
This commit is contained in:
commit
f448e9c9da
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@ -70,12 +70,36 @@ static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
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static u16 dmaor_read(struct sh_dmae_device *shdev)
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{
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return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
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u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
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if (shdev->pdata->dmaor_is_32bit)
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return __raw_readl(addr);
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else
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return __raw_readw(addr);
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}
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static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
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{
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__raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
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u32 __iomem *addr = shdev->chan_reg + DMAOR / sizeof(u32);
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if (shdev->pdata->dmaor_is_32bit)
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__raw_writel(data, addr);
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else
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__raw_writew(data, addr);
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}
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static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data)
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{
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struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
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__raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32));
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}
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static u32 chcr_read(struct sh_dmae_chan *sh_dc)
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{
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struct sh_dmae_device *shdev = to_sh_dev(sh_dc);
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return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32));
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}
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/*
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@ -120,7 +144,7 @@ static int sh_dmae_rst(struct sh_dmae_device *shdev)
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static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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u32 chcr = chcr_read(sh_chan);
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if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE)
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return true; /* working */
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@ -167,18 +191,23 @@ static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
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static void dmae_start(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
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u32 chcr = chcr_read(sh_chan);
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chcr |= CHCR_DE | CHCR_IE;
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sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR);
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if (shdev->pdata->needs_tend_set)
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sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND);
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chcr |= CHCR_DE | shdev->chcr_ie_bit;
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chcr_write(sh_chan, chcr & ~CHCR_TE);
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}
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static void dmae_halt(struct sh_dmae_chan *sh_chan)
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{
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u32 chcr = sh_dmae_readl(sh_chan, CHCR);
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struct sh_dmae_device *shdev = to_sh_dev(sh_chan);
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u32 chcr = chcr_read(sh_chan);
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chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
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sh_dmae_writel(sh_chan, chcr, CHCR);
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chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit);
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chcr_write(sh_chan, chcr);
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}
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static void dmae_init(struct sh_dmae_chan *sh_chan)
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@ -190,7 +219,7 @@ static void dmae_init(struct sh_dmae_chan *sh_chan)
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u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
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LOG2_DEFAULT_XFER_SIZE);
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sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
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sh_dmae_writel(sh_chan, chcr, CHCR);
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chcr_write(sh_chan, chcr);
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}
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static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
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@ -200,7 +229,7 @@ static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
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return -EBUSY;
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sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
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sh_dmae_writel(sh_chan, val, CHCR);
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chcr_write(sh_chan, val);
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return 0;
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}
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@ -216,6 +245,9 @@ static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
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if (dmae_is_busy(sh_chan))
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return -EBUSY;
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if (pdata->no_dmars)
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return 0;
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/* in the case of a missing DMARS resource use first memory window */
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if (!addr)
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addr = (u16 __iomem *)shdev->chan_reg;
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@ -840,7 +872,7 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data)
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spin_lock(&sh_chan->desc_lock);
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chcr = sh_dmae_readl(sh_chan, CHCR);
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chcr = chcr_read(sh_chan);
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if (chcr & CHCR_TE) {
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/* DMA stop */
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@ -1138,6 +1170,16 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
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/* platform data */
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shdev->pdata = pdata;
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if (pdata->chcr_offset)
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shdev->chcr_offset = pdata->chcr_offset;
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else
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shdev->chcr_offset = CHCR;
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if (pdata->chcr_ie_bit)
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shdev->chcr_ie_bit = pdata->chcr_ie_bit;
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else
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shdev->chcr_ie_bit = CHCR_IE;
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platform_set_drvdata(pdev, shdev);
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pm_runtime_enable(&pdev->dev);
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@ -47,6 +47,8 @@ struct sh_dmae_device {
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struct list_head node;
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u32 __iomem *chan_reg;
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u16 __iomem *dmars;
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unsigned int chcr_offset;
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u32 chcr_ie_bit;
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};
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#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
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@ -62,6 +62,12 @@ struct sh_dmae_pdata {
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const unsigned int *ts_shift;
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int ts_shift_num;
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u16 dmaor_init;
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unsigned int chcr_offset;
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u32 chcr_ie_bit;
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unsigned int dmaor_is_32bit:1;
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unsigned int needs_tend_set:1;
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unsigned int no_dmars:1;
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};
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/* DMA register */
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@ -71,6 +77,8 @@ struct sh_dmae_pdata {
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#define CHCR 0x0C
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#define DMAOR 0x40
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#define TEND 0x18 /* USB-DMAC */
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004
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#define DMAOR_NMIF 0x00000002
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