[PATCH] bcm43xx: add PCI-E code
The current bcm43xx driver does not contain code to handle PCI-E interfaces such as the BCM4311 and BCM4312. This patch, originally written by Stefano Brivio adds the necessary code to enable these interfaces. Signed-off-by: Stefano Brivio <stefano.brivio@polimi.it> Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Stefano Brivio
Jeff Garzik
parent
995cdaa45b
commit
f3d1fca3eb
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@ -159,6 +159,7 @@
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/* Chipcommon registers. */
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#define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04
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#define BCM43xx_CHIPCOMMON_CTL 0x28
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#define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0
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#define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4
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#define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8
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@ -172,6 +173,33 @@
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/* SBTOPCI2 values. */
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#define BCM43xx_SBTOPCI2_PREFETCH 0x4
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#define BCM43xx_SBTOPCI2_BURST 0x8
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#define BCM43xx_SBTOPCI2_MEMREAD_MULTI 0x20
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/* PCI-E core registers. */
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#define BCM43xx_PCIECORE_REG_ADDR 0x0130
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#define BCM43xx_PCIECORE_REG_DATA 0x0134
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#define BCM43xx_PCIECORE_MDIO_CTL 0x0128
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#define BCM43xx_PCIECORE_MDIO_DATA 0x012C
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/* PCI-E registers. */
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#define BCM43xx_PCIE_TLP_WORKAROUND 0x0004
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#define BCM43xx_PCIE_DLLP_LINKCTL 0x0100
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/* PCI-E MDIO bits. */
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#define BCM43xx_PCIE_MDIO_ST 0x40000000
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#define BCM43xx_PCIE_MDIO_WT 0x10000000
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#define BCM43xx_PCIE_MDIO_DEV 22
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#define BCM43xx_PCIE_MDIO_REG 18
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#define BCM43xx_PCIE_MDIO_TA 0x00020000
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#define BCM43xx_PCIE_MDIO_TC 0x0100
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/* MDIO devices. */
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#define BCM43xx_MDIO_SERDES_RX 0x1F
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/* SERDES RX registers. */
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#define BCM43xx_SERDES_RXTIMER 0x2
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#define BCM43xx_SERDES_CDR 0x6
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#define BCM43xx_SERDES_CDR_BW 0x7
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/* Chipcommon capabilities. */
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#define BCM43xx_CAPABILITIES_PCTL 0x00040000
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@ -221,6 +249,7 @@
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#define BCM43xx_COREID_USB20_HOST 0x819
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#define BCM43xx_COREID_USB20_DEV 0x81a
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#define BCM43xx_COREID_SDIO_HOST 0x81b
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#define BCM43xx_COREID_PCIE 0x820
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/* Core Information Registers */
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#define BCM43xx_CIR_BASE 0xf00
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@ -130,6 +130,10 @@ MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
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{ PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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/* Broadcom 4307 802.11b */
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{ PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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/* Broadcom 4311 802.11(a)/b/g */
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{ PCI_VENDOR_ID_BROADCOM, 0x4311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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/* Broadcom 4312 802.11a/b/g */
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{ PCI_VENDOR_ID_BROADCOM, 0x4312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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/* Broadcom 4318 802.11b/g */
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{ PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
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/* Broadcom 4319 802.11a/b/g */
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@ -2600,8 +2604,9 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
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/* fetch sb_id_hi from core information registers */
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sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
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core_id = (sb_id_hi & 0xFFF0) >> 4;
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core_rev = (sb_id_hi & 0xF);
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core_id = (sb_id_hi & 0x8FF0) >> 4;
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core_rev = (sb_id_hi & 0x7000) >> 8;
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core_rev |= (sb_id_hi & 0xF);
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core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
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/* if present, chipcommon is always core 0; read the chipid from it */
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@ -2711,6 +2716,7 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
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core = NULL;
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switch (core_id) {
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case BCM43xx_COREID_PCI:
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case BCM43xx_COREID_PCIE:
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core = &bcm->core_pci;
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if (core->available) {
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printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
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@ -2749,12 +2755,12 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
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case 6:
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case 7:
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case 9:
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case 10:
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break;
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default:
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printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
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printk(KERN_WARNING PFX
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"Unsupported 80211 core revision %u\n",
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core_rev);
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err = -ENODEV;
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goto out;
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}
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bcm->nr_80211_available++;
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core->priv = ext_80211;
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@ -2868,16 +2874,11 @@ static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
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u32 sbimconfiglow;
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u8 limit;
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if (bcm->chip_rev < 5) {
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if (bcm->core_pci.rev <= 5 && bcm->core_pci.id != BCM43xx_COREID_PCIE) {
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sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
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sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
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sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
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if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
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sbimconfiglow |= 0x32;
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else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
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sbimconfiglow |= 0x53;
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else
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assert(0);
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sbimconfiglow |= 0x32;
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bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
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}
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@ -3004,22 +3005,64 @@ static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
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static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
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{
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int err;
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struct bcm43xx_coreinfo *old_core;
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int err = 0;
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old_core = bcm->current_core;
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err = bcm43xx_switch_core(bcm, &bcm->core_pci);
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if (err)
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goto out;
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bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
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bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
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if (bcm->core_chipcommon.available) {
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err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
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if (err)
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goto out;
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bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
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/* this function is always called when a PCI core is mapped */
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err = bcm43xx_switch_core(bcm, &bcm->core_pci);
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if (err)
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goto out;
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} else
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bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
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bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
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bcm43xx_switch_core(bcm, old_core);
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assert(err == 0);
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out:
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return err;
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}
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static u32 bcm43xx_pcie_reg_read(struct bcm43xx_private *bcm, u32 address)
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{
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bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
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return bcm43xx_read32(bcm, BCM43xx_PCIECORE_REG_DATA);
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}
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static void bcm43xx_pcie_reg_write(struct bcm43xx_private *bcm, u32 address,
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u32 data)
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{
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bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_ADDR, address);
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bcm43xx_write32(bcm, BCM43xx_PCIECORE_REG_DATA, data);
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}
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static void bcm43xx_pcie_mdio_write(struct bcm43xx_private *bcm, u8 dev, u8 reg,
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u16 data)
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{
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int i;
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bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0x0082);
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bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_DATA, BCM43xx_PCIE_MDIO_ST |
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BCM43xx_PCIE_MDIO_WT | (dev << BCM43xx_PCIE_MDIO_DEV) |
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(reg << BCM43xx_PCIE_MDIO_REG) | BCM43xx_PCIE_MDIO_TA |
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data);
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udelay(10);
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for (i = 0; i < 10; i++) {
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if (bcm43xx_read32(bcm, BCM43xx_PCIECORE_MDIO_CTL) &
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BCM43xx_PCIE_MDIO_TC)
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break;
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msleep(1);
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}
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bcm43xx_write32(bcm, BCM43xx_PCIECORE_MDIO_CTL, 0);
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}
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/* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
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* To enable core 0, pass a core_mask of 1<<0
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*/
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@ -3039,7 +3082,8 @@ static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
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if (err)
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goto out;
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if (bcm->core_pci.rev < 6) {
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if (bcm->current_core->rev < 6 ||
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bcm->current_core->id == BCM43xx_COREID_PCI) {
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value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
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value |= (1 << backplane_flag_nr);
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bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
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@ -3057,21 +3101,46 @@ static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
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}
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}
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value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
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value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
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bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
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if (bcm->current_core->id == BCM43xx_COREID_PCI) {
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value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
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value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
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bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
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if (bcm->core_pci.rev < 5) {
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value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
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value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
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& BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
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value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
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& BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
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bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
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err = bcm43xx_pcicore_commit_settings(bcm);
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assert(err == 0);
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if (bcm->current_core->rev < 5) {
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value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
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value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
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& BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
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value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
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& BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
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bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
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err = bcm43xx_pcicore_commit_settings(bcm);
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assert(err == 0);
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} else if (bcm->current_core->rev >= 11) {
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value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
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value |= BCM43xx_SBTOPCI2_MEMREAD_MULTI;
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bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
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}
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} else {
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if (bcm->current_core->rev == 0 || bcm->current_core->rev == 1) {
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value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_TLP_WORKAROUND);
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value |= 0x8;
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bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_TLP_WORKAROUND,
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value);
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}
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if (bcm->current_core->rev == 0) {
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bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
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BCM43xx_SERDES_RXTIMER, 0x8128);
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bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
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BCM43xx_SERDES_CDR, 0x0100);
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bcm43xx_pcie_mdio_write(bcm, BCM43xx_MDIO_SERDES_RX,
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BCM43xx_SERDES_CDR_BW, 0x1466);
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} else if (bcm->current_core->rev == 1) {
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value = bcm43xx_pcie_reg_read(bcm, BCM43xx_PCIE_DLLP_LINKCTL);
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value |= 0x40;
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bcm43xx_pcie_reg_write(bcm, BCM43xx_PCIE_DLLP_LINKCTL,
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value);
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}
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}
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out_switch_back:
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err = bcm43xx_switch_core(bcm, old_core);
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out:
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@ -3676,7 +3745,7 @@ static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
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bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
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break;
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case BCM43xx_PHYTYPE_G:
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if (phy_rev > 7)
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if (phy_rev > 8)
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phy_rev_ok = 0;
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bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
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IEEE80211_CCK_MODULATION;
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@ -153,8 +153,6 @@ int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
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int err, maxfreq;
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struct bcm43xx_coreinfo *old_core;
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if (!(bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL))
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return 0;
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old_core = bcm->current_core;
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err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
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if (err == -ENODEV)
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@ -162,11 +160,27 @@ int bcm43xx_pctl_init(struct bcm43xx_private *bcm)
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if (err)
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goto out;
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maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1);
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY,
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(maxfreq * 150 + 999999) / 1000000);
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY,
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(maxfreq * 15 + 999999) / 1000000);
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if (bcm->chip_id == 0x4321) {
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if (bcm->chip_rev == 0)
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_CTL, 0x03A4);
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if (bcm->chip_rev == 1)
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_CTL, 0x00A4);
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}
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if (bcm->chipcommon_capabilities & BCM43xx_CAPABILITIES_PCTL) {
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if (bcm->current_core->rev >= 10) {
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/* Set Idle Power clock rate to 1Mhz */
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL,
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(bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_SYSCLKCTL)
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& 0x0000FFFF) | 0x40000);
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} else {
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maxfreq = bcm43xx_pctl_clockfreqlimit(bcm, 1);
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_PLLONDELAY,
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(maxfreq * 150 + 999999) / 1000000);
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bcm43xx_write32(bcm, BCM43xx_CHIPCOMMON_FREFSELDELAY,
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(maxfreq * 15 + 999999) / 1000000);
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}
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}
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err = bcm43xx_switch_core(bcm, old_core);
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assert(err == 0);
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