Merge branch 'clk-hi3519' into clk-next
* clk-hi3519: clk: hisilicon: add CRG driver for hi3519 soc clk: hisilicon: export some hisilicon APIs to modules reset: hisilicon: add reset controller driver for hisilicon SOCs
This commit is contained in:
Stephen Boyd
commit
f3bf9841b8
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@ -0,0 +1,46 @@
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* Hisilicon Hi3519 Clock and Reset Generator(CRG)
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The Hi3519 CRG module provides clock and reset signals to various
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controllers within the SoC.
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This binding uses the following bindings:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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Documentation/devicetree/bindings/reset/reset.txt
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Required Properties:
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- compatible: should be one of the following.
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- "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
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- #reset-cells: should be 2.
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A reset signal can be controlled by writing a bit register in the CRG module.
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The reset specifier consists of two cells. The first cell represents the
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register offset relative to the base address. The second cell represents the
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bit index in the register.
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Example: CRG nodes
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CRG: clock-reset-controller@12010000 {
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compatible = "hisilicon,hi3519-crg";
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reg = <0x12010000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <2>;
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};
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Example: consumer nodes
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i2c0: i2c@12110000 {
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compatible = "hisilicon,hi3519-i2c";
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reg = <0x12110000 0x1000>;
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clocks = <&CRG HI3519_I2C0_RST>;
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resets = <&CRG 0xe4 0>;
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};
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@ -1,3 +1,11 @@
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config COMMON_CLK_HI3519
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tristate "Hi3519 Clock Driver"
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depends on ARCH_HISI || COMPILE_TEST
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select RESET_HISI
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default ARCH_HISI
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help
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Build the clock driver for hi3519.
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config COMMON_CLK_HI6220
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bool "Hi6220 Clock Driver"
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depends on ARCH_HISI || COMPILE_TEST
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@ -5,6 +13,13 @@ config COMMON_CLK_HI6220
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help
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Build the Hisilicon Hi6220 clock driver based on the common clock framework.
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config RESET_HISI
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bool "HiSilicon Reset Controller Driver"
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depends on ARCH_HISI || COMPILE_TEST
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select RESET_CONTROLLER
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help
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Build reset controller driver for HiSilicon device chipsets.
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config STUB_CLK_HI6220
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bool "Hi6220 Stub Clock Driver"
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depends on COMMON_CLK_HI6220 && MAILBOX
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@ -7,5 +7,7 @@ obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
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obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
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obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
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obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
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obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
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obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
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obj-$(CONFIG_RESET_HISI) += reset.o
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obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
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@ -0,0 +1,131 @@
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/*
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* Hi3519 Clock Driver
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*
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* Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <dt-bindings/clock/hi3519-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk.h"
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#include "reset.h"
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#define HI3519_INNER_CLK_OFFSET 64
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#define HI3519_FIXED_24M 65
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#define HI3519_FIXED_50M 66
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#define HI3519_FIXED_75M 67
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#define HI3519_FIXED_125M 68
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#define HI3519_FIXED_150M 69
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#define HI3519_FIXED_200M 70
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#define HI3519_FIXED_250M 71
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#define HI3519_FIXED_300M 72
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#define HI3519_FIXED_400M 73
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#define HI3519_FMC_MUX 74
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#define HI3519_NR_CLKS 128
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static const struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] = {
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{ HI3519_FIXED_24M, "24m", NULL, 0, 24000000, },
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{ HI3519_FIXED_50M, "50m", NULL, 0, 50000000, },
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{ HI3519_FIXED_75M, "75m", NULL, 0, 75000000, },
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{ HI3519_FIXED_125M, "125m", NULL, 0, 125000000, },
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{ HI3519_FIXED_150M, "150m", NULL, 0, 150000000, },
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{ HI3519_FIXED_200M, "200m", NULL, 0, 200000000, },
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{ HI3519_FIXED_250M, "250m", NULL, 0, 250000000, },
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{ HI3519_FIXED_300M, "300m", NULL, 0, 300000000, },
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{ HI3519_FIXED_400M, "400m", NULL, 0, 400000000, },
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};
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static const char *const fmc_mux_p[] = {
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"24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
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static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
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static const struct hisi_mux_clock hi3519_mux_clks[] = {
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{ HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
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CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
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};
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static const struct hisi_gate_clock hi3519_gate_clks[] = {
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{ HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
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CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
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{ HI3519_UART0_CLK, "clk_uart0", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
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{ HI3519_UART1_CLK, "clk_uart1", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
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{ HI3519_UART2_CLK, "clk_uart2", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
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{ HI3519_UART3_CLK, "clk_uart3", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
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{ HI3519_UART4_CLK, "clk_uart4", "24m",
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CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
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{ HI3519_SPI0_CLK, "clk_spi0", "50m",
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CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
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{ HI3519_SPI1_CLK, "clk_spi1", "50m",
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CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
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{ HI3519_SPI2_CLK, "clk_spi2", "50m",
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CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
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};
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static int hi3519_clk_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct hisi_clock_data *clk_data;
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struct hisi_reset_controller *rstc;
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rstc = hisi_reset_init(np);
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if (!rstc)
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return -ENOMEM;
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clk_data = hisi_clk_init(np, HI3519_NR_CLKS);
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if (!clk_data) {
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hisi_reset_exit(rstc);
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return -ENODEV;
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}
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hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
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ARRAY_SIZE(hi3519_fixed_rate_clks),
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clk_data);
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hisi_clk_register_mux(hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks),
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clk_data);
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hisi_clk_register_gate(hi3519_gate_clks,
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ARRAY_SIZE(hi3519_gate_clks), clk_data);
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return 0;
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}
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static const struct of_device_id hi3519_clk_match_table[] = {
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{ .compatible = "hisilicon,hi3519-crg" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, hi3519_clk_match_table);
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static struct platform_driver hi3519_clk_driver = {
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.probe = hi3519_clk_probe,
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.driver = {
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.name = "hi3519-clk",
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.of_match_table = hi3519_clk_match_table,
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},
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};
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static int __init hi3519_clk_init(void)
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{
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return platform_driver_register(&hi3519_clk_driver);
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}
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core_initcall(hi3519_clk_init);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver");
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@ -37,7 +37,7 @@
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static DEFINE_SPINLOCK(hisi_clk_lock);
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struct hisi_clock_data __init *hisi_clk_init(struct device_node *np,
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struct hisi_clock_data *hisi_clk_init(struct device_node *np,
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int nr_clks)
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{
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struct hisi_clock_data *clk_data;
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@ -71,8 +71,9 @@ err_data:
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err:
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return NULL;
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}
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EXPORT_SYMBOL_GPL(hisi_clk_init);
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void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
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void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
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int nums, struct hisi_clock_data *data)
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{
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struct clk *clk;
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@ -91,8 +92,9 @@ void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
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data->clk_data.clks[clks[i].id] = clk;
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}
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}
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EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_rate);
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void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
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void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
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int nums,
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struct hisi_clock_data *data)
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{
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@ -112,8 +114,9 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
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data->clk_data.clks[clks[i].id] = clk;
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}
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}
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EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor);
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void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
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void hisi_clk_register_mux(const struct hisi_mux_clock *clks,
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int nums, struct hisi_clock_data *data)
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{
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struct clk *clk;
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@ -141,8 +144,9 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
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data->clk_data.clks[clks[i].id] = clk;
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}
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}
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EXPORT_SYMBOL_GPL(hisi_clk_register_mux);
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void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
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void hisi_clk_register_divider(const struct hisi_divider_clock *clks,
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int nums, struct hisi_clock_data *data)
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{
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struct clk *clk;
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@ -170,8 +174,9 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
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data->clk_data.clks[clks[i].id] = clk;
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}
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}
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EXPORT_SYMBOL_GPL(hisi_clk_register_divider);
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void __init hisi_clk_register_gate(struct hisi_gate_clock *clks,
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void hisi_clk_register_gate(const struct hisi_gate_clock *clks,
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int nums, struct hisi_clock_data *data)
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{
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struct clk *clk;
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@ -198,8 +203,9 @@ void __init hisi_clk_register_gate(struct hisi_gate_clock *clks,
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data->clk_data.clks[clks[i].id] = clk;
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}
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}
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EXPORT_SYMBOL_GPL(hisi_clk_register_gate);
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void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
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void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks,
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int nums, struct hisi_clock_data *data)
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{
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struct clk *clk;
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@ -226,8 +232,9 @@ void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
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data->clk_data.clks[clks[i].id] = clk;
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}
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}
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EXPORT_SYMBOL_GPL(hisi_clk_register_gate_sep);
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void __init hi6220_clk_register_divider(struct hi6220_divider_clock *clks,
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void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks,
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int nums, struct hisi_clock_data *data)
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{
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struct clk *clk;
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|
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@ -111,18 +111,18 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
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u8 shift, u8 width, u32 mask_bit, spinlock_t *lock);
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struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
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void hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *,
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void hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *,
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int, struct hisi_clock_data *);
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void hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *,
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void hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *,
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int, struct hisi_clock_data *);
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void hisi_clk_register_mux(struct hisi_mux_clock *, int,
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void hisi_clk_register_mux(const struct hisi_mux_clock *, int,
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struct hisi_clock_data *);
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void hisi_clk_register_divider(struct hisi_divider_clock *,
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void hisi_clk_register_divider(const struct hisi_divider_clock *,
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int, struct hisi_clock_data *);
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void hisi_clk_register_gate(struct hisi_gate_clock *,
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void hisi_clk_register_gate(const struct hisi_gate_clock *,
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int, struct hisi_clock_data *);
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void hisi_clk_register_gate_sep(struct hisi_gate_clock *,
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void hisi_clk_register_gate_sep(const struct hisi_gate_clock *,
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int, struct hisi_clock_data *);
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void hi6220_clk_register_divider(struct hi6220_divider_clock *,
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void hi6220_clk_register_divider(const struct hi6220_divider_clock *,
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int, struct hisi_clock_data *);
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#endif /* __HISI_CLK_H */
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|
|
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|
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@ -0,0 +1,134 @@
|
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/*
|
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* Hisilicon Reset Controller Driver
|
||||
*
|
||||
* Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/reset-controller.h>
|
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#include <linux/slab.h>
|
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#include <linux/spinlock.h>
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#include "reset.h"
|
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|
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#define HISI_RESET_BIT_MASK 0x1f
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#define HISI_RESET_OFFSET_SHIFT 8
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#define HISI_RESET_OFFSET_MASK 0xffff00
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|
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struct hisi_reset_controller {
|
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spinlock_t lock;
|
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void __iomem *membase;
|
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struct reset_controller_dev rcdev;
|
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};
|
||||
|
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|
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#define to_hisi_reset_controller(rcdev) \
|
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container_of(rcdev, struct hisi_reset_controller, rcdev)
|
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|
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static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev,
|
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const struct of_phandle_args *reset_spec)
|
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{
|
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u32 offset;
|
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u8 bit;
|
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|
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offset = (reset_spec->args[0] << HISI_RESET_OFFSET_SHIFT)
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& HISI_RESET_OFFSET_MASK;
|
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bit = reset_spec->args[1] & HISI_RESET_BIT_MASK;
|
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|
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return (offset | bit);
|
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}
|
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|
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static int hisi_reset_assert(struct reset_controller_dev *rcdev,
|
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unsigned long id)
|
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{
|
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struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
|
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unsigned long flags;
|
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u32 offset, reg;
|
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u8 bit;
|
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|
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offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
|
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bit = id & HISI_RESET_BIT_MASK;
|
||||
|
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spin_lock_irqsave(&rstc->lock, flags);
|
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|
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reg = readl(rstc->membase + offset);
|
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writel(reg | BIT(bit), rstc->membase + offset);
|
||||
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spin_unlock_irqrestore(&rstc->lock, flags);
|
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|
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return 0;
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}
|
||||
|
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static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
|
||||
unsigned long flags;
|
||||
u32 offset, reg;
|
||||
u8 bit;
|
||||
|
||||
offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
|
||||
bit = id & HISI_RESET_BIT_MASK;
|
||||
|
||||
spin_lock_irqsave(&rstc->lock, flags);
|
||||
|
||||
reg = readl(rstc->membase + offset);
|
||||
writel(reg & ~BIT(bit), rstc->membase + offset);
|
||||
|
||||
spin_unlock_irqrestore(&rstc->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct reset_control_ops hisi_reset_ops = {
|
||||
.assert = hisi_reset_assert,
|
||||
.deassert = hisi_reset_deassert,
|
||||
};
|
||||
|
||||
struct hisi_reset_controller *hisi_reset_init(struct device_node *np)
|
||||
{
|
||||
struct hisi_reset_controller *rstc;
|
||||
|
||||
rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
|
||||
if (!rstc)
|
||||
return NULL;
|
||||
|
||||
rstc->membase = of_iomap(np, 0);
|
||||
if (!rstc->membase) {
|
||||
kfree(rstc);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
spin_lock_init(&rstc->lock);
|
||||
|
||||
rstc->rcdev.owner = THIS_MODULE;
|
||||
rstc->rcdev.ops = &hisi_reset_ops;
|
||||
rstc->rcdev.of_node = np;
|
||||
rstc->rcdev.of_reset_n_cells = 2;
|
||||
rstc->rcdev.of_xlate = hisi_reset_of_xlate;
|
||||
reset_controller_register(&rstc->rcdev);
|
||||
|
||||
return rstc;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hisi_reset_init);
|
||||
|
||||
void hisi_reset_exit(struct hisi_reset_controller *rstc)
|
||||
{
|
||||
reset_controller_unregister(&rstc->rcdev);
|
||||
iounmap(rstc->membase);
|
||||
kfree(rstc);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(hisi_reset_exit);
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __HISI_RESET_H
|
||||
#define __HISI_RESET_H
|
||||
|
||||
struct device_node;
|
||||
struct hisi_reset_controller;
|
||||
|
||||
#ifdef CONFIG_RESET_CONTROLLER
|
||||
struct hisi_reset_controller *hisi_reset_init(struct device_node *np);
|
||||
void hisi_reset_exit(struct hisi_reset_controller *rstc);
|
||||
#else
|
||||
static inline hisi_reset_controller *hisi_reset_init(struct device_node *np)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void hisi_reset_exit(struct hisi_reset_controller *rstc)
|
||||
{}
|
||||
#endif
|
||||
|
||||
#endif /* __HISI_RESET_H */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __DTS_HI3519_CLOCK_H
|
||||
#define __DTS_HI3519_CLOCK_H
|
||||
|
||||
#define HI3519_FMC_CLK 1
|
||||
#define HI3519_SPI0_CLK 2
|
||||
#define HI3519_SPI1_CLK 3
|
||||
#define HI3519_SPI2_CLK 4
|
||||
#define HI3519_UART0_CLK 5
|
||||
#define HI3519_UART1_CLK 6
|
||||
#define HI3519_UART2_CLK 7
|
||||
#define HI3519_UART3_CLK 8
|
||||
#define HI3519_UART4_CLK 9
|
||||
#define HI3519_PWM_CLK 10
|
||||
#define HI3519_DMA_CLK 11
|
||||
#define HI3519_IR_CLK 12
|
||||
#define HI3519_ETH_PHY_CLK 13
|
||||
#define HI3519_ETH_MAC_CLK 14
|
||||
#define HI3519_ETH_MACIF_CLK 15
|
||||
#define HI3519_USB2_BUS_CLK 16
|
||||
#define HI3519_USB2_PORT_CLK 17
|
||||
#define HI3519_USB3_CLK 18
|
||||
|
||||
#endif /* __DTS_HI3519_CLOCK_H */
|
||||
Loading…
Reference in New Issue