staging: rtl8188eu: remove more unused defines
Remove some defines for register addresses and bits which obviously refer to chipsets other than rtl8188eu. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Link: https://lore.kernel.org/r/20210620175301.14988-13-martin@kaiser.cx Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Martin Kaiser
Greg Kroah-Hartman
parent
0684c15d32
commit
f38143580e
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@ -7,15 +7,8 @@
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#ifndef __RTL8188E_SPEC_H__
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#define __RTL8188E_SPEC_H__
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/* 8192C Register offset definition */
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#define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */
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#define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */
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#define MAC_ADDR_LEN 6
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/* 8188E PKT_BUFF_ACCESS_CTRL value */
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#define TXPKT_BUF_SELECT 0x69
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#define RXPKT_BUF_SELECT 0xA5
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#define DISABLE_TRXPKT_BUF_ACCESS 0x0
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/* 0x0000h ~ 0x00FFh System Configuration */
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@ -52,19 +45,7 @@
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#define REG_FSISR 0x0054
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#define REG_HSIMR 0x0058
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#define REG_HSISR 0x005c
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#define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS
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* Multi-Function GPIO Pin Control.
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*/
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#define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS
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* Multi-Function GPIO Select.
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*/
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#define REG_BB_PAD_CTRL 0x0064
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#define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS
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* Multi-Function control source.
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*/
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#define REG_GPIO_OUTPUT 0x006c
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#define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */
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#define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */
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#define REG_MCUFWDL 0x0080
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#define REG_WOL_EVENT 0x0081 /* RTL8188E */
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#define REG_MCUTSTCFG 0x0084
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@ -172,9 +153,6 @@
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#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */
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#define REG_WATCH_DOG 0x0368
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/* RTL8723 series ------------------------------ */
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#define REG_PCIE_HISR 0x03A0
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/* spec version 11 */
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/* 0x0400h ~ 0x047Fh Protocol Configuration */
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#define REG_VOQ_INFORMATION 0x0400
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@ -459,34 +437,6 @@
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#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2)
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#define GPIO_MOD (REG_GPIO_PIN_CTRL + 3)
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/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
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#define HSIMR_GPIO12_0_INT_EN BIT(0)
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#define HSIMR_SPS_OCP_INT_EN BIT(5)
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#define HSIMR_RON_INT_EN BIT(6)
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#define HSIMR_PDN_INT_EN BIT(7)
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#define HSIMR_GPIO9_INT_EN BIT(25)
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/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
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#define HSISR_GPIO12_0_INT BIT(0)
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#define HSISR_SPS_OCP_INT BIT(5)
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#define HSISR_RON_INT_EN BIT(6)
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#define HSISR_PDNINT BIT(7)
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#define HSISR_GPIO9_INT BIT(25)
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/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */
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/*
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* Network Type
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* 00: No link
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* 01: Link in ad hoc network
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* 10: Link in infrastructure network
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* 11: AP mode
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* Default: 00b.
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*/
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#define MSR_NOLINK 0x00
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#define MSR_ADHOC 0x01
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#define MSR_INFRA 0x02
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#define MSR_AP 0x03
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/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */
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#define USB_INTR_CONTENT_C2H_OFFSET 0
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#define USB_INTR_CONTENT_CPWM1_OFFSET 16
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@ -505,34 +455,6 @@
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#define CMD_EFUSE_PATCH_ERR BIT(6)
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#define CMD_IOCONFIG_ERR BIT(7)
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/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
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/* 8192C Response Rate Set Register (offset 0x181, 24bits) */
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#define RRSR_1M BIT(0)
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#define RRSR_2M BIT(1)
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#define RRSR_5_5M BIT(2)
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#define RRSR_11M BIT(3)
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#define RRSR_6M BIT(4)
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#define RRSR_9M BIT(5)
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#define RRSR_12M BIT(6)
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#define RRSR_18M BIT(7)
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#define RRSR_24M BIT(8)
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#define RRSR_36M BIT(9)
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#define RRSR_48M BIT(10)
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#define RRSR_54M BIT(11)
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#define RRSR_MCS0 BIT(12)
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#define RRSR_MCS1 BIT(13)
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#define RRSR_MCS2 BIT(14)
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#define RRSR_MCS3 BIT(15)
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#define RRSR_MCS4 BIT(16)
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#define RRSR_MCS5 BIT(17)
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#define RRSR_MCS6 BIT(18)
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#define RRSR_MCS7 BIT(19)
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/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */
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/* WOL bit information */
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#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
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#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
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/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
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#define BW_OPMODE_20MHZ BIT(2)
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#define BW_OPMODE_5G BIT(1)
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@ -565,12 +487,6 @@
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#define SCR_TxSecEnable 0x02
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#define SCR_RxSecEnable 0x04
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/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
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#define WOW_PMEN BIT(0) /* Power management Enable. */
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#define WOW_WOMEN BIT(1) /* WoW function on or off. */
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#define WOW_MAGIC BIT(2) /* Magic packet */
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#define WOW_UWF BIT(3) /* Unicast Wakeup frame. */
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/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */
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/* 8188 IMR/ISR bits */
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#define IMR_DISABLED_88E 0x0
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@ -648,21 +564,6 @@ So the following defines for 92C is not entire!!!!!!
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* 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
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* 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
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*/
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/* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */
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/* Note:
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* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet
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* RTL8192S/RTL8192C are wrong,
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* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2,
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* and BK - Bit3.
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* 8723 and 88E may be not correct either in the earlier version.
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*/
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#define StopBecon BIT(6)
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#define StopHigh BIT(5)
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#define StopMgt BIT(4)
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#define StopBK BIT(3)
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#define StopBE BIT(2)
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#define StopVI BIT(1)
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#define StopVO BIT(0)
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/* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */
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#define RCR_APPFCS BIT(31) /* WMAC append FCS after payload */
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@ -695,14 +596,8 @@ So the following defines for 92C is not entire!!!!!!
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#define RCR_FIFO_OFFSET 13
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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#define REG_USB_INFO 0xFE17
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#define REG_USB_SPECIAL_OPTION 0xFE55
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#define REG_USB_DMA_AGG_TO 0xFE5B
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#define REG_USB_AGG_TO 0xFE5C
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#define REG_USB_AGG_TH 0xFE5D
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#define REG_USB_HRPWM 0xFE58
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#define REG_USB_HCPWM 0xFE57
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/* 8192C Register Bit and Content definition */
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/* 0x0000h ~ 0x00FFh System Configuration */
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@ -1140,14 +1035,6 @@ So the following defines for 92C is not entire!!!!!!
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/* GPS function enable */
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#define GPS_FUNC_EN BIT(22)
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/* 3 REG_LIFECTRL_CTRL */
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#define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3)
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#define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2)
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#define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1)
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#define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0)
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#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */
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/* General definitions */
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#define LAST_ENTRY_OF_TX_PKT_BUFFER 176 /* 22k 22528 bytes */
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@ -1173,48 +1060,15 @@ So the following defines for 92C is not entire!!!!!!
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#define EEPROM_CUSTOMERID_88E 0xC5
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#define EEPROM_RF_ANTENNA_OPT_88E 0xC9
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/* RTL88EE */
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#define EEPROM_MAC_ADDR_88EE 0xD0
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#define EEPROM_VID_88EE 0xD6
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#define EEPROM_DID_88EE 0xD8
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#define EEPROM_SVID_88EE 0xDA
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#define EEPROM_SMID_88EE 0xDC
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/* RTL88EU */
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#define EEPROM_MAC_ADDR_88EU 0xD7
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#define EEPROM_VID_88EU 0xD0
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#define EEPROM_PID_88EU 0xD2
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#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4
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/* RTL88ES */
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#define EEPROM_MAC_ADDR_88ES 0x11A
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/* EEPROM/Efuse Value Type */
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#define EETYPE_TX_PWR 0x0
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/* Default Value for EEPROM or EFUSE!!! */
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#define EEPROM_Default_TSSI 0x0
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#define EEPROM_Default_TxPowerDiff 0x0
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#define EEPROM_Default_CrystalCap 0x5
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/* Default: 2X2, RTL8192CE(QFPN68) */
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#define EEPROM_Default_BoardType 0x02
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#define EEPROM_Default_TxPower 0x1010
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#define EEPROM_Default_HT2T_TxPwr 0x10
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#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
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#define EEPROM_Default_ThermalMeter 0x12
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#define EEPROM_Default_AntTxPowerDiff 0x0
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#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
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#define EEPROM_Default_TxPowerLevel 0x2A
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#define EEPROM_Default_HT40_2SDiff 0x0
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/* HT20<->40 default Tx Power Index Difference */
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#define EEPROM_Default_HT20_Diff 2
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#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
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#define EEPROM_Default_HT40_PwrMaxOffset 0
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#define EEPROM_Default_HT20_PwrMaxOffset 0
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#define EEPROM_Default_CrystalCap_88E 0x20
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#define EEPROM_Default_ThermalMeter_88E 0x18
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