[ARM] nommu: add ARM946E-S core support
This patch adds ARM946E-S core support which has typically 8KB I&D cache. It has a MPU and supports ARMv5TE instruction set. Because the ARM946E-S core can be synthesizable with various cache size, CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Hyok S. Choi
Russell King
parent
d60674eb5d
commit
f37f46eb1c
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@ -60,6 +60,7 @@ tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi
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tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi
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tune-$(CONFIG_CPU_ARM9TDMI) :=-mtune=arm9tdmi
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tune-$(CONFIG_CPU_ARM940T) :=-mtune=arm9tdmi
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tune-$(CONFIG_CPU_ARM946T) :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
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tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi
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tune-$(CONFIG_CPU_ARM922T) :=-mtune=arm9tdmi
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tune-$(CONFIG_CPU_ARM925T) :=-mtune=arm9tdmi
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@ -200,6 +200,21 @@ config CPU_ARM940T
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Say Y if you want support for the ARM940T processor.
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Otherwise, say N.
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# ARM946E-S
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config CPU_ARM946E
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bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
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select CPU_32v5
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select CPU_ABRT_EV5T
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select CPU_CACHE_VIVT
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select CPU_CP15_MPU
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help
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ARM946E-S is a member of the ARM9E-S family of high-
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performance, 32-bit system-on-chip processor solutions.
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The TCM and ARMv5TE 32-bit instruction set is supported.
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Say Y if you want support for the ARM946E-S processor.
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Otherwise, say N.
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# ARM1020 - needs validating
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config CPU_ARM1020
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bool "Support ARM1020T (rev 0) processor"
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@ -480,7 +495,7 @@ comment "Processor Features"
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config ARM_THUMB
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bool "Support Thumb user binaries"
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depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
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depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
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default y
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help
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Say Y if you want to include kernel support for running user space
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@ -515,9 +530,22 @@ config CPU_DCACHE_DISABLE
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Say Y here to disable the processor data cache. Unless
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you have a reason not to or are unsure, say N.
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config CPU_DCACHE_SIZE
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hex
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depends on CPU_ARM740T || CPU_ARM946E
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default 0x00001000 if CPU_ARM740T
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default 0x00002000 # default size for ARM946E-S
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help
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Some cores are synthesizable to have various sized cache. For
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ARM946E-S case, it can vary from 0KB to 1MB.
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To support such cache operations, it is efficient to know the size
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before compile time.
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If your SoC is configured to have a different size, define the value
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here with proper conditions.
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config CPU_DCACHE_WRITETHROUGH
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bool "Force write through D-cache"
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depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
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depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
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default y if CPU_ARM925T
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help
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Say Y here to use the data cache in writethrough mode. Unless you
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@ -525,7 +553,7 @@ config CPU_DCACHE_WRITETHROUGH
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config CPU_CACHE_ROUND_ROBIN
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bool "Round robin I and D cache replacement algorithm"
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depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
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depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
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help
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Say Y here to use the predictable round-robin cache replacement
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policy. Unless you specifically require this or are unsure, say N.
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@ -55,6 +55,7 @@ obj-$(CONFIG_CPU_ARM922T) += proc-arm922.o
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obj-$(CONFIG_CPU_ARM925T) += proc-arm925.o
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obj-$(CONFIG_CPU_ARM926T) += proc-arm926.o
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obj-$(CONFIG_CPU_ARM940T) += proc-arm940.o
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obj-$(CONFIG_CPU_ARM946E) += proc-arm946.o
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obj-$(CONFIG_CPU_ARM1020) += proc-arm1020.o
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obj-$(CONFIG_CPU_ARM1020E) += proc-arm1020e.o
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obj-$(CONFIG_CPU_ARM1022) += proc-arm1022.o
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@ -0,0 +1,424 @@
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/*
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* linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
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*
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* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
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*
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* (Many of cache codes are from proc-arm926.S)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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/*
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* ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
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* comprising 256 lines of 32 bytes (8 words).
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*/
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#define CACHE_DSIZE (CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
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#define CACHE_DLINESIZE 32 /* fixed */
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#define CACHE_DSEGMENTS 4 /* fixed */
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#define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
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#define CACHE_DLIMIT (CACHE_DSIZE * 4) /* benchmark needed */
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.text
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/*
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* cpu_arm946_proc_init()
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* cpu_arm946_switch_mm()
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*
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* These are not required.
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*/
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ENTRY(cpu_arm946_proc_init)
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ENTRY(cpu_arm946_switch_mm)
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mov pc, lr
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/*
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* cpu_arm946_proc_fin()
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*/
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ENTRY(cpu_arm946_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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bl arm946_flush_kern_cache_all
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x00001000 @ i-cache
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bic r0, r0, #0x00000004 @ d-cache
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ldmfd sp!, {pc}
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/*
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* cpu_arm946_reset(loc)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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ENTRY(cpu_arm946_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ flush I cache
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x00000005 @ .............c.p
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bic ip, ip, #0x00001000 @ i-cache
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_arm946_do_idle()
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*/
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.align 5
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ENTRY(cpu_arm946_do_idle)
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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/*
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* flush_user_cache_all()
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*/
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ENTRY(arm946_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(arm946_flush_kern_cache_all)
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mov r2, #VM_EXEC
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mov ip, #0
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__flush_whole_cache:
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache
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#else
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mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
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subs r3, r3, #1 << 4
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bcs 2b @ entries n to 0
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subs r1, r1, #1 << 29
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bcs 1b @ segments 3 to 0
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#endif
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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* (same as arm926)
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*/
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ENTRY(arm946_flush_user_cache_range)
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mov ip, #0
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bhs __flush_whole_cache
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1: tst r2, #VM_EXEC
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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#else
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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#endif
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm946_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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* (same as arm926)
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*/
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ENTRY(arm946_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - page aligned address
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* (same as arm926)
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*/
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ENTRY(arm946_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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* (same as arm926)
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*/
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ENTRY(arm946_dma_inv_range)
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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#endif
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as arm926)
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*/
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ENTRY(arm946_dma_clean_range)
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as arm926)
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*/
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ENTRY(arm946_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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#else
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mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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#endif
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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ENTRY(arm946_cache_fns)
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.long arm946_flush_kern_cache_all
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.long arm946_flush_user_cache_all
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.long arm946_flush_user_cache_range
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.long arm946_coherent_kern_range
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.long arm946_coherent_user_range
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.long arm946_flush_kern_dcache_page
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.long arm946_dma_inv_range
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.long arm946_dma_clean_range
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.long arm946_dma_flush_range
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ENTRY(cpu_arm946_dcache_clean_area)
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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subs r1, r1, #CACHE_DLINESIZE
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bhi 1b
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#endif
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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__INIT
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.type __arm946_setup, #function
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__arm946_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
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mcr p15, 0, r0, c6, c4, 0
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mcr p15, 0, r0, c6, c5, 0
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mcr p15, 0, r0, c6, c6, 0
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mcr p15, 0, r0, c6, c7, 0
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mov r0, #0x0000003F @ base = 0, size = 4GB
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mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
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ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
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ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
|
||||
mov r2, #10 @ 11 is the minimum (4KB)
|
||||
1: add r2, r2, #1 @ area size *= 2
|
||||
mov r1, r1, lsr #1
|
||||
bne 1b @ count not zero r-shift
|
||||
orr r0, r0, r2, lsl #1 @ the region register value
|
||||
orr r0, r0, #1 @ set enable bit
|
||||
mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
|
||||
|
||||
ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
|
||||
ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
|
||||
mov r2, #10 @ 11 is the minimum (4KB)
|
||||
1: add r2, r2, #1 @ area size *= 2
|
||||
mov r1, r1, lsr #1
|
||||
bne 1b @ count not zero r-shift
|
||||
orr r0, r0, r2, lsl #1 @ the region register value
|
||||
orr r0, r0, #1 @ set enable bit
|
||||
mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
|
||||
|
||||
mov r0, #0x06
|
||||
mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
|
||||
mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
|
||||
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
|
||||
mov r0, #0x00 @ disable whole write buffer
|
||||
#else
|
||||
mov r0, #0x02 @ region 1 write bufferred
|
||||
#endif
|
||||
mcr p15, 0, r0, c3, c0, 0
|
||||
|
||||
/*
|
||||
* Access Permission Settings for future permission control by PU.
|
||||
*
|
||||
* priv. user
|
||||
* region 0 (whole) rw -- : b0001
|
||||
* region 1 (RAM) rw rw : b0011
|
||||
* region 2 (FLASH) rw r- : b0010
|
||||
* region 3~7 (none) -- -- : b0000
|
||||
*/
|
||||
mov r0, #0x00000031
|
||||
orr r0, r0, #0x00000200
|
||||
mcr p15, 0, r0, c5, c0, 2 @ set data access permission
|
||||
mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
|
||||
|
||||
mrc p15, 0, r0, c1, c0 @ get control register
|
||||
orr r0, r0, #0x00001000 @ I-cache
|
||||
orr r0, r0, #0x00000005 @ MPU/D-cache
|
||||
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
|
||||
orr r0, r0, #0x00004000 @ .1.. .... .... ....
|
||||
#endif
|
||||
mov pc, lr
|
||||
|
||||
.size __arm946_setup, . - __arm946_setup
|
||||
|
||||
__INITDATA
|
||||
|
||||
/*
|
||||
* Purpose : Function pointers used to access above functions - all calls
|
||||
* come through these
|
||||
*/
|
||||
.type arm946_processor_functions, #object
|
||||
ENTRY(arm946_processor_functions)
|
||||
.word v5t_early_abort
|
||||
.word cpu_arm946_proc_init
|
||||
.word cpu_arm946_proc_fin
|
||||
.word cpu_arm946_reset
|
||||
.word cpu_arm946_do_idle
|
||||
|
||||
.word cpu_arm946_dcache_clean_area
|
||||
.word cpu_arm946_switch_mm
|
||||
.word 0 @ cpu_*_set_pte
|
||||
.size arm946_processor_functions, . - arm946_processor_functions
|
||||
|
||||
.section ".rodata"
|
||||
|
||||
.type cpu_arch_name, #object
|
||||
cpu_arch_name:
|
||||
.asciz "armv5te"
|
||||
.size cpu_arch_name, . - cpu_arch_name
|
||||
|
||||
.type cpu_elf_name, #object
|
||||
cpu_elf_name:
|
||||
.asciz "v5t"
|
||||
.size cpu_elf_name, . - cpu_elf_name
|
||||
|
||||
.type cpu_arm946_name, #object
|
||||
cpu_arm946_name:
|
||||
.ascii "ARM946E-S"
|
||||
.size cpu_arm946_name, . - cpu_arm946_name
|
||||
|
||||
.align
|
||||
|
||||
.section ".proc.info.init", #alloc, #execinstr
|
||||
.type __arm946_proc_info,#object
|
||||
__arm946_proc_info:
|
||||
.long 0x41009460
|
||||
.long 0xff00fff0
|
||||
.long 0
|
||||
b __arm946_setup
|
||||
.long cpu_arch_name
|
||||
.long cpu_elf_name
|
||||
.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
|
||||
.long cpu_arm946_name
|
||||
.long arm946_processor_functions
|
||||
.long 0
|
||||
.long 0
|
||||
.long arm940_cache_fns
|
||||
.size __arm946_proc_info, . - __arm946_proc_info
|
||||
|
||||
|
|
@ -64,6 +64,14 @@
|
|||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_ARM946E)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
# else
|
||||
# define _CACHE arm946
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
|
|
|
|||
|
|
@ -113,6 +113,14 @@
|
|||
# define CPU_NAME cpu_arm940
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_ARM946E
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
# define MULTI_CPU
|
||||
# else
|
||||
# define CPU_NAME cpu_arm946
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_SA110
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
|
|
|
|||
Loading…
Reference in New Issue