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drm/i915/d13: Add Wa_16015201720 disabling clock gating for PIPEDMC-A/B 

Add a workaround making sure that PIPEDMC-A/B is enabled when the
firmware needs these on D13 platforms to save/restore the registers
backed by the PW_1 and PW_A power wells.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220727164523.1621361-2-imre.deak@intel.com
This commit is contained in:
Imre Deak 2022-07-27 19:45:23 +03:00
parent fa6a4cdeaf
commit f31bccd398
2 changed files with 15 additions and 0 deletions
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8
drivers/gpu/drm/i915/display/intel_display_power.c
View File

@ -1615,6 +1615,14 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
/* Wa_16015201720:adl-p,dg2 */
if (DISPLAY_VER(dev_priv) == 13) {
intel_de_rmw(dev_priv, CLKGATE_DIS_PSL_EXT(PIPE_A),
0, PIPEDMC_GATING_DIS);
intel_de_rmw(dev_priv, CLKGATE_DIS_PSL_EXT(PIPE_B),
0, PIPEDMC_GATING_DIS);
}
/* 1. Enable PCH reset handshake. */
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));

7
drivers/gpu/drm/i915/i915_reg.h
View File

@ -1892,6 +1892,13 @@
#define CLKGATE_DIS_PSL(pipe) \
_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
#define _CLKGATE_DIS_PSL_EXT_B 0x46550
#define PIPEDMC_GATING_DIS REG_BIT(12)
#define CLKGATE_DIS_PSL_EXT(pipe) \
_MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
/*
* Display engine regs
*/