parisc: flush pages through tmpalias space
The kernel has an 8M tmpailas space (originally designed for copying and clearing pages but now only used for clearing). The idea is to place zeros into the cache above a physical page rather than into the physical page and flush the cache, because often the zeros end up being replaced quickly anyway. We can also use the tmpalias space for flushing a page. The difference here is that we have to do tmpalias processing in the non access data and instruction traps. The principle is the same: as long as we know the physical address and have a virtual address congruent to the real one, the flush will be effective. In order to use the tmpalias space, the icache miss path has to be enhanced to check for the alias region to make the fic instruction effective. Signed-off-by: James Bottomley <James.Bottomley@suse.de>
This commit is contained in:
James Bottomley
James Bottomley
parent
38567333a6
commit
f311847c2f
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@ -26,8 +26,6 @@ void flush_user_dcache_range_asm(unsigned long, unsigned long);
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void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
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void flush_kernel_dcache_page_asm(void *);
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void flush_kernel_icache_page(void *);
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void flush_user_dcache_page(unsigned long);
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void flush_user_icache_page(unsigned long);
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void flush_user_dcache_range(unsigned long, unsigned long);
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void flush_user_icache_range(unsigned long, unsigned long);
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@ -90,12 +88,15 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned
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void flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end);
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/* defined in pacache.S exported in cache.c used by flush_anon_page */
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void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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#define ARCH_HAS_FLUSH_ANON_PAGE
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static inline void
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flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
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{
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if (PageAnon(page))
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flush_user_dcache_page(vmaddr);
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flush_dcache_page_asm(page_to_phys(page), vmaddr);
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}
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#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
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@ -27,12 +27,17 @@
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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#include <asm/sections.h>
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#include <asm/shmparam.h>
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int split_tlb __read_mostly;
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int dcache_stride __read_mostly;
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int icache_stride __read_mostly;
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EXPORT_SYMBOL(dcache_stride);
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void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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EXPORT_SYMBOL(flush_dcache_page_asm);
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void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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/* On some machines (e.g. ones with the Merced bus), there can be
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* only a single PxTLB broadcast at a time; this must be guaranteed
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@ -259,81 +264,13 @@ void disable_sr_hashing(void)
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panic("SpaceID hashing is still on!\n");
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}
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/* Simple function to work out if we have an existing address translation
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* for a user space vma. */
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static inline int translation_exists(struct vm_area_struct *vma,
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unsigned long addr, unsigned long pfn)
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{
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pgd_t *pgd = pgd_offset(vma->vm_mm, addr);
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pmd_t *pmd;
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pte_t pte;
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if(pgd_none(*pgd))
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return 0;
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pmd = pmd_offset(pgd, addr);
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if(pmd_none(*pmd) || pmd_bad(*pmd))
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return 0;
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/* We cannot take the pte lock here: flush_cache_page is usually
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* called with pte lock already held. Whereas flush_dcache_page
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* takes flush_dcache_mmap_lock, which is lower in the hierarchy:
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* the vma itself is secure, but the pte might come or go racily.
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*/
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pte = *pte_offset_map(pmd, addr);
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/* But pte_unmap() does nothing on this architecture */
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/* Filter out coincidental file entries and swap entries */
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if (!(pte_val(pte) & (_PAGE_FLUSH|_PAGE_PRESENT)))
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return 0;
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return pte_pfn(pte) == pfn;
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}
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/* Private function to flush a page from the cache of a non-current
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* process. cr25 contains the Page Directory of the current user
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* process; we're going to hijack both it and the user space %sr3 to
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* temporarily make the non-current process current. We have to do
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* this because cache flushing may cause a non-access tlb miss which
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* the handlers have to fill in from the pgd of the non-current
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* process. */
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static inline void
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flush_user_cache_page_non_current(struct vm_area_struct *vma,
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unsigned long vmaddr)
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__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
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unsigned long physaddr)
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{
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/* save the current process space and pgd */
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unsigned long space = mfsp(3), pgd = mfctl(25);
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/* we don't mind taking interrupts since they may not
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* do anything with user space, but we can't
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* be preempted here */
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preempt_disable();
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/* make us current */
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mtctl(__pa(vma->vm_mm->pgd), 25);
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mtsp(vma->vm_mm->context, 3);
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flush_user_dcache_page(vmaddr);
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flush_dcache_page_asm(physaddr, vmaddr);
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if (vma->vm_flags & VM_EXEC)
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flush_user_icache_page(vmaddr);
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/* put the old current process back */
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mtsp(space, 3);
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mtctl(pgd, 25);
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preempt_enable();
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}
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static inline void
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__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr)
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{
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if (likely(vma->vm_mm->context == mfsp(3))) {
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flush_user_dcache_page(vmaddr);
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if (vma->vm_flags & VM_EXEC)
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flush_user_icache_page(vmaddr);
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} else {
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flush_user_cache_page_non_current(vma, vmaddr);
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}
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flush_icache_page_asm(physaddr, vmaddr);
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}
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void flush_dcache_page(struct page *page)
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@ -342,10 +279,8 @@ void flush_dcache_page(struct page *page)
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struct vm_area_struct *mpnt;
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struct prio_tree_iter iter;
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unsigned long offset;
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unsigned long addr;
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unsigned long addr, old_addr = 0;
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pgoff_t pgoff;
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unsigned long pfn = page_to_pfn(page);
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if (mapping && !mapping_mapped(mapping)) {
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set_bit(PG_dcache_dirty, &page->flags);
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@ -369,20 +304,11 @@ void flush_dcache_page(struct page *page)
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offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
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addr = mpnt->vm_start + offset;
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/* Flush instructions produce non access tlb misses.
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* On PA, we nullify these instructions rather than
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* taking a page fault if the pte doesn't exist.
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* This is just for speed. If the page translation
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* isn't there, there's no point exciting the
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* nadtlb handler into a nullification frenzy.
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*
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* Make sure we really have this page: the private
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* mappings may cover this area but have COW'd this
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* particular page.
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*/
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if (translation_exists(mpnt, addr, pfn)) {
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__flush_cache_page(mpnt, addr);
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break;
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if (old_addr == 0 || (old_addr & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
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__flush_cache_page(mpnt, addr, page_to_phys(page));
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if (old_addr)
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printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
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old_addr = addr;
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}
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}
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flush_dcache_mmap_unlock(mapping);
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@ -573,7 +499,6 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long
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{
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BUG_ON(!vma->vm_mm->context);
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if (likely(translation_exists(vma, vmaddr, pfn)))
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__flush_cache_page(vma, vmaddr);
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__flush_cache_page(vma, vmaddr, page_to_phys(pfn_to_page(pfn)));
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}
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@ -225,22 +225,13 @@
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#ifndef CONFIG_64BIT
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/*
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* naitlb miss interruption handler (parisc 1.1 - 32 bit)
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*
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* Note: naitlb misses will be treated
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* as an ordinary itlb miss for now.
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* However, note that naitlb misses
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* have the faulting address in the
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* IOR/ISR.
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*/
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.macro naitlb_11 code
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mfctl %isr,spc
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b itlb_miss_11
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b naitlb_miss_11
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mfctl %ior,va
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/* FIXME: If user causes a naitlb miss, the priv level may not be in
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* lower bits of va, where the itlb miss handler is expecting them
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*/
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.align 32
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.endm
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@ -248,26 +239,17 @@
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/*
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* naitlb miss interruption handler (parisc 2.0)
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*
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* Note: naitlb misses will be treated
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* as an ordinary itlb miss for now.
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* However, note that naitlb misses
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* have the faulting address in the
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* IOR/ISR.
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*/
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.macro naitlb_20 code
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mfctl %isr,spc
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#ifdef CONFIG_64BIT
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b itlb_miss_20w
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b naitlb_miss_20w
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#else
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b itlb_miss_20
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b naitlb_miss_20
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#endif
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mfctl %ior,va
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/* FIXME: If user causes a naitlb miss, the priv level may not be in
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* lower bits of va, where the itlb miss handler is expecting them
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*/
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.align 32
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.endm
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@ -581,7 +563,24 @@
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copy \va,\tmp1
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depi 0,31,23,\tmp1
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cmpb,COND(<>),n \tmp,\tmp1,\fault
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ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),\prot
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mfctl %cr19,\tmp /* iir */
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/* get the opcode (first six bits) into \tmp */
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extrw,u \tmp,5,6,\tmp
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/*
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* Only setting the T bit prevents data cache movein
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* Setting access rights to zero prevents instruction cache movein
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*
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* Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
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* to type field and _PAGE_READ goes to top bit of PL1
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*/
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ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
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/*
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* so if the opcode is one (i.e. this is a memory management
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* instruction) nullify the next load so \prot is only T.
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* Otherwise this is a normal data operation
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*/
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cmpiclr,= 0x01,\tmp,%r0
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ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
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depd,z \prot,8,7,\prot
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/*
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* OK, it is in the temp alias region, check whether "from" or "to".
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@ -631,11 +630,7 @@ ENTRY(fault_vector_20)
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def 13
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def 14
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dtlb_20 15
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#if 0
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naitlb_20 16
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#else
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def 16
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#endif
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nadtlb_20 17
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def 18
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def 19
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@ -678,11 +673,7 @@ ENTRY(fault_vector_11)
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def 13
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def 14
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dtlb_11 15
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#if 0
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naitlb_11 16
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#else
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def 16
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#endif
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nadtlb_11 17
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def 18
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def 19
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@ -1203,7 +1194,7 @@ nadtlb_miss_20w:
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get_pgd spc,ptp
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space_check spc,t0,nadtlb_fault
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L3_ptep ptp,pte,t0,va,nadtlb_check_flush_20w
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L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
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update_ptep ptp,pte,t0,t1
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@ -1214,6 +1205,14 @@ nadtlb_miss_20w:
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rfir
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nop
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nadtlb_check_alias_20w:
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do_alias spc,t0,t1,va,pte,prot,nadtlb_check_flush_20w
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idtlbt pte,prot
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rfir
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nop
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nadtlb_check_flush_20w:
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bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
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@ -1255,25 +1254,7 @@ dtlb_miss_11:
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nop
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dtlb_check_alias_11:
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/* Check to see if fault is in the temporary alias region */
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cmpib,<>,n 0,spc,dtlb_fault /* forward */
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ldil L%(TMPALIAS_MAP_START),t0
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copy va,t1
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depwi 0,31,23,t1
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cmpb,<>,n t0,t1,dtlb_fault /* forward */
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ldi (_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),prot
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depw,z prot,8,7,prot
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/*
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* OK, it is in the temp alias region, check whether "from" or "to".
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* Check "subtle" note in pacache.S re: r23/r26.
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*/
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extrw,u,= va,9,1,r0
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or,tr %r23,%r0,pte /* If "from" use "from" page */
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or %r26,%r0,pte /* else "to", use "to" page */
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do_alias spc,t0,t1,va,pte,prot,dtlb_fault
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idtlba pte,(va)
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idtlbp prot,(va)
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@ -1286,7 +1267,7 @@ nadtlb_miss_11:
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space_check spc,t0,nadtlb_fault
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L2_ptep ptp,pte,t0,va,nadtlb_check_flush_11
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L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
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update_ptep ptp,pte,t0,t1
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@ -1304,6 +1285,15 @@ nadtlb_miss_11:
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rfir
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nop
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nadtlb_check_alias_11:
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do_alias spc,t0,t1,va,pte,prot,nadtlb_check_flush_11
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idtlba pte,(va)
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idtlbp prot,(va)
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rfir
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nop
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nadtlb_check_flush_11:
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bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
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@ -1359,7 +1349,7 @@ nadtlb_miss_20:
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space_check spc,t0,nadtlb_fault
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L2_ptep ptp,pte,t0,va,nadtlb_check_flush_20
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L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
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update_ptep ptp,pte,t0,t1
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@ -1372,6 +1362,14 @@ nadtlb_miss_20:
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rfir
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nop
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nadtlb_check_alias_20:
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do_alias spc,t0,t1,va,pte,prot,nadtlb_check_flush_20
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idtlbt pte,prot
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rfir
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nop
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nadtlb_check_flush_20:
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bb,>=,n pte,_PAGE_FLUSH_BIT,nadtlb_emulate
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@ -1484,6 +1482,36 @@ itlb_miss_20w:
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rfir
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nop
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naitlb_miss_20w:
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/*
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* I miss is a little different, since we allow users to fault
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* on the gateway page which is in the kernel address space.
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*/
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space_adjust spc,va,t0
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get_pgd spc,ptp
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space_check spc,t0,naitlb_fault
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L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
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update_ptep ptp,pte,t0,t1
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make_insert_tlb spc,pte,prot
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iitlbt pte,prot
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rfir
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nop
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naitlb_check_alias_20w:
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do_alias spc,t0,t1,va,pte,prot,naitlb_fault
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iitlbt pte,prot
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rfir
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nop
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#else
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itlb_miss_11:
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@ -1508,6 +1536,38 @@ itlb_miss_11:
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rfir
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nop
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naitlb_miss_11:
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get_pgd spc,ptp
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space_check spc,t0,naitlb_fault
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L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
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update_ptep ptp,pte,t0,t1
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make_insert_tlb_11 spc,pte,prot
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mfsp %sr1,t0 /* Save sr1 so we can use it in tlb inserts */
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mtsp spc,%sr1
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iitlba pte,(%sr1,va)
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iitlbp prot,(%sr1,va)
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mtsp t0, %sr1 /* Restore sr1 */
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rfir
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nop
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naitlb_check_alias_11:
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do_alias spc,t0,t1,va,pte,prot,itlb_fault
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iitlba pte,(%sr0, va)
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iitlbp prot,(%sr0, va)
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rfir
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nop
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||||
itlb_miss_20:
|
||||
get_pgd spc,ptp
|
||||
|
||||
|
|
@ -1526,6 +1586,32 @@ itlb_miss_20:
|
|||
rfir
|
||||
nop
|
||||
|
||||
naitlb_miss_20:
|
||||
get_pgd spc,ptp
|
||||
|
||||
space_check spc,t0,naitlb_fault
|
||||
|
||||
L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
|
||||
|
||||
update_ptep ptp,pte,t0,t1
|
||||
|
||||
make_insert_tlb spc,pte,prot
|
||||
|
||||
f_extend pte,t0
|
||||
|
||||
iitlbt pte,prot
|
||||
|
||||
rfir
|
||||
nop
|
||||
|
||||
naitlb_check_alias_20:
|
||||
do_alias spc,t0,t1,va,pte,prot,naitlb_fault
|
||||
|
||||
iitlbt pte,prot
|
||||
|
||||
rfir
|
||||
nop
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
|
|
@ -1662,6 +1748,10 @@ nadtlb_fault:
|
|||
b intr_save
|
||||
ldi 17,%r8
|
||||
|
||||
naitlb_fault:
|
||||
b intr_save
|
||||
ldi 16,%r8
|
||||
|
||||
dtlb_fault:
|
||||
b intr_save
|
||||
ldi 15,%r8
|
||||
|
|
|
|||
|
|
@ -608,6 +608,130 @@ ENTRY(__clear_user_page_asm)
|
|||
.procend
|
||||
ENDPROC(__clear_user_page_asm)
|
||||
|
||||
ENTRY(flush_dcache_page_asm)
|
||||
.proc
|
||||
.callinfo NO_CALLS
|
||||
.entry
|
||||
|
||||
ldil L%(TMPALIAS_MAP_START), %r28
|
||||
#ifdef CONFIG_64BIT
|
||||
#if (TMPALIAS_MAP_START >= 0x80000000)
|
||||
depdi 0, 31,32, %r28 /* clear any sign extension */
|
||||
/* FIXME: page size dependend */
|
||||
#endif
|
||||
extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
|
||||
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
|
||||
depdi 0, 63,12, %r28 /* Clear any offset bits */
|
||||
#else
|
||||
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
|
||||
depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
|
||||
depwi 0, 31,12, %r28 /* Clear any offset bits */
|
||||
#endif
|
||||
|
||||
/* Purge any old translation */
|
||||
|
||||
pdtlb 0(%r28)
|
||||
|
||||
ldil L%dcache_stride, %r1
|
||||
ldw R%dcache_stride(%r1), %r1
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
depdi,z 1, 63-PAGE_SHIFT,1, %r25
|
||||
#else
|
||||
depwi,z 1, 31-PAGE_SHIFT,1, %r25
|
||||
#endif
|
||||
add %r28, %r25, %r25
|
||||
sub %r25, %r1, %r25
|
||||
|
||||
|
||||
1: fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
fdc,m %r1(%r28)
|
||||
cmpb,COND(<<) %r28, %r25,1b
|
||||
fdc,m %r1(%r28)
|
||||
|
||||
sync
|
||||
bv %r0(%r2)
|
||||
pdtlb (%r25)
|
||||
.exit
|
||||
|
||||
.procend
|
||||
ENDPROC(flush_dcache_page_asm)
|
||||
|
||||
ENTRY(flush_icache_page_asm)
|
||||
.proc
|
||||
.callinfo NO_CALLS
|
||||
.entry
|
||||
|
||||
ldil L%(TMPALIAS_MAP_START), %r28
|
||||
#ifdef CONFIG_64BIT
|
||||
#if (TMPALIAS_MAP_START >= 0x80000000)
|
||||
depdi 0, 31,32, %r28 /* clear any sign extension */
|
||||
/* FIXME: page size dependend */
|
||||
#endif
|
||||
extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
|
||||
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
|
||||
depdi 0, 63,12, %r28 /* Clear any offset bits */
|
||||
#else
|
||||
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
|
||||
depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
|
||||
depwi 0, 31,12, %r28 /* Clear any offset bits */
|
||||
#endif
|
||||
|
||||
/* Purge any old translation */
|
||||
|
||||
pitlb (%sr0,%r28)
|
||||
|
||||
ldil L%icache_stride, %r1
|
||||
ldw R%icache_stride(%r1), %r1
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
depdi,z 1, 63-PAGE_SHIFT,1, %r25
|
||||
#else
|
||||
depwi,z 1, 31-PAGE_SHIFT,1, %r25
|
||||
#endif
|
||||
add %r28, %r25, %r25
|
||||
sub %r25, %r1, %r25
|
||||
|
||||
|
||||
1: fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
fic,m %r1(%r28)
|
||||
cmpb,COND(<<) %r28, %r25,1b
|
||||
fic,m %r1(%r28)
|
||||
|
||||
sync
|
||||
bv %r0(%r2)
|
||||
pitlb (%sr0,%r25)
|
||||
.exit
|
||||
|
||||
.procend
|
||||
ENDPROC(flush_icache_page_asm)
|
||||
|
||||
ENTRY(flush_kernel_dcache_page_asm)
|
||||
.proc
|
||||
.callinfo NO_CALLS
|
||||
|
|
@ -651,93 +775,6 @@ ENTRY(flush_kernel_dcache_page_asm)
|
|||
.procend
|
||||
ENDPROC(flush_kernel_dcache_page_asm)
|
||||
|
||||
ENTRY(flush_user_dcache_page)
|
||||
.proc
|
||||
.callinfo NO_CALLS
|
||||
.entry
|
||||
|
||||
ldil L%dcache_stride, %r1
|
||||
ldw R%dcache_stride(%r1), %r23
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
depdi,z 1,63-PAGE_SHIFT,1, %r25
|
||||
#else
|
||||
depwi,z 1,31-PAGE_SHIFT,1, %r25
|
||||
#endif
|
||||
add %r26, %r25, %r25
|
||||
sub %r25, %r23, %r25
|
||||
|
||||
|
||||
1: fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
cmpb,COND(<<) %r26, %r25,1b
|
||||
fdc,m %r23(%sr3, %r26)
|
||||
|
||||
sync
|
||||
bv %r0(%r2)
|
||||
nop
|
||||
.exit
|
||||
|
||||
.procend
|
||||
ENDPROC(flush_user_dcache_page)
|
||||
|
||||
ENTRY(flush_user_icache_page)
|
||||
.proc
|
||||
.callinfo NO_CALLS
|
||||
.entry
|
||||
|
||||
ldil L%dcache_stride, %r1
|
||||
ldw R%dcache_stride(%r1), %r23
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
depdi,z 1, 63-PAGE_SHIFT,1, %r25
|
||||
#else
|
||||
depwi,z 1, 31-PAGE_SHIFT,1, %r25
|
||||
#endif
|
||||
add %r26, %r25, %r25
|
||||
sub %r25, %r23, %r25
|
||||
|
||||
|
||||
1: fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
fic,m %r23(%sr3, %r26)
|
||||
cmpb,COND(<<) %r26, %r25,1b
|
||||
fic,m %r23(%sr3, %r26)
|
||||
|
||||
sync
|
||||
bv %r0(%r2)
|
||||
nop
|
||||
.exit
|
||||
|
||||
.procend
|
||||
ENDPROC(flush_user_icache_page)
|
||||
|
||||
|
||||
ENTRY(purge_kernel_dcache_page)
|
||||
.proc
|
||||
.callinfo NO_CALLS
|
||||
|
|
@ -780,69 +817,6 @@ ENTRY(purge_kernel_dcache_page)
|
|||
.procend
|
||||
ENDPROC(purge_kernel_dcache_page)
|
||||
|
||||
#if 0
|
||||
/* Currently not used, but it still is a possible alternate
|
||||
* solution.
|
||||
*/
|
||||
|
||||
ENTRY(flush_alias_page)
|
||||
.proc
|
||||
.callinfo NO_CALLS
|
||||
.entry
|
||||
|
||||
tophys_r1 %r26
|
||||
|
||||
ldil L%(TMPALIAS_MAP_START), %r28
|
||||
#ifdef CONFIG_64BIT
|
||||
extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
|
||||
depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
|
||||
depdi 0, 63,12, %r28 /* Clear any offset bits */
|
||||
#else
|
||||
extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
|
||||
depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
|
||||
depwi 0, 31,12, %r28 /* Clear any offset bits */
|
||||
#endif
|
||||
|
||||
/* Purge any old translation */
|
||||
|
||||
pdtlb 0(%r28)
|
||||
|
||||
ldil L%dcache_stride, %r1
|
||||
ldw R%dcache_stride(%r1), %r23
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
depdi,z 1, 63-PAGE_SHIFT,1, %r29
|
||||
#else
|
||||
depwi,z 1, 31-PAGE_SHIFT,1, %r29
|
||||
#endif
|
||||
add %r28, %r29, %r29
|
||||
sub %r29, %r23, %r29
|
||||
|
||||
1: fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
fdc,m %r23(%r28)
|
||||
cmpb,COND(<<) %r28, %r29, 1b
|
||||
fdc,m %r23(%r28)
|
||||
|
||||
sync
|
||||
bv %r0(%r2)
|
||||
nop
|
||||
.exit
|
||||
|
||||
.procend
|
||||
#endif
|
||||
|
||||
.export flush_user_dcache_range_asm
|
||||
|
||||
|
|
@ -865,7 +839,6 @@ flush_user_dcache_range_asm:
|
|||
.exit
|
||||
|
||||
.procend
|
||||
ENDPROC(flush_alias_page)
|
||||
|
||||
ENTRY(flush_kernel_dcache_range_asm)
|
||||
.proc
|
||||
|
|
|
|||
Loading…
Reference in New Issue