[BNX2]: Fix 5706 serdes link down bug.
1. Correct the MII expansion serdes control register definition. 2. Check an additional RUDI_INVALID bit when determining 5706S link. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -5315,7 +5315,7 @@ bnx2_5706_serdes_has_link(struct bnx2 *bp)
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bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
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bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
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if (an_dbg & MISC_SHDW_AN_DBG_NOSYNC)
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if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
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return 0;
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bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
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@ -6346,11 +6346,12 @@ struct l2_fhdr {
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#define MII_BNX2_DSP_EXPAND_REG 0x0f00
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#define MII_EXPAND_REG1 (MII_BNX2_DSP_EXPAND_REG | 1)
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#define MII_EXPAND_REG1_RUDI_C 0x20
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#define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 2)
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#define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 3)
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#define MII_BNX2_MISC_SHADOW 0x1c
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#define MISC_SHDW_AN_DBG 0x6800
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#define MISC_SHDW_AN_DBG_NOSYNC 0x0002
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#define MISC_SHDW_AN_DBG_RUDI_INVALID 0x0100
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#define MISC_SHDW_MODE_CTL 0x7c00
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#define MISC_SHDW_MODE_CTL_SIG_DET 0x0010
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