clk: samsung: exynosautov9: add cmu_peric0 clock support
CMU_PERIC0 provides clocks for USI0 ~ USI5 and USIx_I2C. USI0/1/2/3/4/5 have its own divider but USI_I2Cs share "dout_peric0_usi_i2c" divider. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220504075154.58819-9-chanho61.park@samsung.com
This commit is contained in:
Chanho Park
Sylwester Nawrocki
parent
65165b11ee
commit
f2dd366992
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@ -1134,6 +1134,257 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
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.clk_name = "dout_clkcmu_fsys2_bus",
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};
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/* ---- CMU_PERIC0 --------------------------------------------------------- */
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/* Register Offset definitions for CMU_PERIC0 (0x10200000) */
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#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
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#define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0610
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#define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1000
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#define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1004
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#define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x1008
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#define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x100c
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#define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1010
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#define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1014
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#define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1018
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#define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1800
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#define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1804
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#define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x1808
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#define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x180c
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#define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1810
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#define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1814
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#define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1818
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x2014
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2018
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x2024
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2028
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x202c
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2030
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2034
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2038
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x203c
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2040
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x201c
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2020
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2044
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2048
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
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#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2050
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static const unsigned long peric0_clk_regs[] __initconst = {
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PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
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PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI,
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CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C,
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CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
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CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
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CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
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CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
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CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
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CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
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CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
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};
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/* List of parent clocks for Muxes in CMU_PERIC0 */
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PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_clkcmu_peric0_bus" };
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PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" };
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PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" };
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static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
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MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
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mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
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MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user",
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mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1),
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/* USI00 ~ USI05 */
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MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi",
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mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
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MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi",
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mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
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MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi",
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mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
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MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi",
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mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
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MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi",
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mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
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MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi",
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mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
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/* USI_I2C */
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MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c",
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mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
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};
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static const struct samsung_div_clock peric0_div_clks[] __initconst = {
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/* USI00 ~ USI05 */
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DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi",
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"mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi",
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"mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi",
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"mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi",
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"mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi",
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"mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI,
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0, 4),
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DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi",
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"mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI,
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0, 4),
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/* USI_I2C */
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DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c",
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"mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
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};
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static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
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/* IPCLK */
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GATE(CLK_GOUT_PERIC0_IPCLK_0, "gout_peric0_ipclk_0",
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"dout_peric0_usi00_usi",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_1, "gout_peric0_ipclk_1",
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"dout_peric0_usi_i2c",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_2, "gout_peric0_ipclk_2",
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"dout_peric0_usi01_usi",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_3, "gout_peric0_ipclk_3",
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"dout_peric0_usi_i2c",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_4, "gout_peric0_ipclk_4",
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"dout_peric0_usi02_usi",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_5, "gout_peric0_ipclk_5",
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"dout_peric0_usi_i2c",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_6, "gout_peric0_ipclk_6",
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"dout_peric0_usi03_usi",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_7, "gout_peric0_ipclk_7",
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"dout_peric0_usi_i2c",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_8, "gout_peric0_ipclk_8",
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"dout_peric0_usi04_usi",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_9, "gout_peric0_ipclk_9",
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"dout_peric0_usi_i2c",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_10, "gout_peric0_ipclk_10",
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"dout_peric0_usi05_usi",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_IPCLK_11, "gout_peric0_ipclk_11",
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"dout_peric0_usi_i2c",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
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21, 0, 0),
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/* PCLK */
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GATE(CLK_GOUT_PERIC0_PCLK_0, "gout_peric0_pclk_0",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_PCLK_2, "gout_peric0_pclk_2",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_PCLK_3, "gout_peric0_pclk_3",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_PCLK_4, "gout_peric0_pclk_4",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_PCLK_5, "gout_peric0_pclk_5",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_PCLK_6, "gout_peric0_pclk_6",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_PCLK_7, "gout_peric0_pclk_7",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_PCLK_8, "gout_peric0_pclk_8",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_PCLK_9, "gout_peric0_pclk_9",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
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21, 0, 0),
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GATE(CLK_GOUT_PERIC0_PCLK_10, "gout_peric0_pclk_10",
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"mout_peric0_bus_user",
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CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
|
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21, 0, 0),
|
||||
GATE(CLK_GOUT_PERIC0_PCLK_11, "gout_peric0_pclk_11",
|
||||
"mout_peric0_bus_user",
|
||||
CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
|
||||
21, 0, 0),
|
||||
};
|
||||
|
||||
static const struct samsung_cmu_info peric0_cmu_info __initconst = {
|
||||
.mux_clks = peric0_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
|
||||
.div_clks = peric0_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(peric0_div_clks),
|
||||
.gate_clks = peric0_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
|
||||
.nr_clk_ids = PERIC0_NR_CLK,
|
||||
.clk_regs = peric0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
|
||||
.clk_name = "dout_clkcmu_peric0_bus",
|
||||
};
|
||||
|
||||
/* ---- CMU_PERIS ---------------------------------------------------------- */
|
||||
|
||||
/* Register Offset definitions for CMU_PERIS (0x10020000) */
|
||||
|
|
@ -1202,6 +1453,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
|
|||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-fsys2",
|
||||
.data = &fsys2_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-peric0",
|
||||
.data = &peric0_cmu_info,
|
||||
}, {
|
||||
.compatible = "samsung,exynosautov9-cmu-peris",
|
||||
.data = &peris_cmu_info,
|
||||
|
|
|
|||
Loading…
Reference in New Issue