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drm/i915: Update some flush helpers to take request structures 

Updated intel_emit_post_sync_nonzero_flush(), gen7_render_ring_cs_stall_wa() and
gen8_emit_pipe_control() to take requests instead of rings.

For: VIZ-5115
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Tomas Elf <tomas.elf@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
John Harrison 2015-05-29 17:43:58 +01:00 committed by Daniel Vetter
parent a84c3ae168
commit f2cf1fcc70
1 changed files with 11 additions and 9 deletions
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20
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -214,8 +214,9 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
* really our business. That leaves only stall at scoreboard. * really our business. That leaves only stall at scoreboard.
*/ */
static int static int
intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
{ {
struct intel_engine_cs *ring = req->ring;
u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret; int ret;
@ -258,7 +259,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
int ret; int ret;
/* Force SNB workarounds for PIPE_CONTROL flushes */ /* Force SNB workarounds for PIPE_CONTROL flushes */
ret = intel_emit_post_sync_nonzero_flush(ring); ret = intel_emit_post_sync_nonzero_flush(req);
if (ret) if (ret)
return ret; return ret;
@ -302,8 +303,9 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
} }
static int static int
gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
{ {
struct intel_engine_cs *ring = req->ring;
int ret; int ret;
ret = intel_ring_begin(ring, 4); ret = intel_ring_begin(ring, 4);
@ -366,7 +368,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
/* Workaround: we must issue a pipe_control with CS-stall bit /* Workaround: we must issue a pipe_control with CS-stall bit
* set before a pipe_control command that has the state cache * set before a pipe_control command that has the state cache
* invalidate bit set. */ * invalidate bit set. */
gen7_render_ring_cs_stall_wa(ring); gen7_render_ring_cs_stall_wa(req);
} }
ret = intel_ring_begin(ring, 4); ret = intel_ring_begin(ring, 4);
@ -383,9 +385,10 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
} }
static int static int
gen8_emit_pipe_control(struct intel_engine_cs *ring, gen8_emit_pipe_control(struct drm_i915_gem_request *req,
u32 flags, u32 scratch_addr) u32 flags, u32 scratch_addr)
{ {
struct intel_engine_cs *ring = req->ring;
int ret; int ret;
ret = intel_ring_begin(ring, 6); ret = intel_ring_begin(ring, 6);
@ -407,9 +410,8 @@ static int
gen8_render_ring_flush(struct drm_i915_gem_request *req, gen8_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains) u32 invalidate_domains, u32 flush_domains)
{ {
struct intel_engine_cs *ring = req->ring;
u32 flags = 0; u32 flags = 0;
u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret; int ret;
flags |= PIPE_CONTROL_CS_STALL; flags |= PIPE_CONTROL_CS_STALL;
@ -429,7 +431,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
/* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
ret = gen8_emit_pipe_control(ring, ret = gen8_emit_pipe_control(req,
PIPE_CONTROL_CS_STALL | PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD, PIPE_CONTROL_STALL_AT_SCOREBOARD,
0); 0);
@ -437,7 +439,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
return ret; return ret;
} }
return gen8_emit_pipe_control(ring, flags, scratch_addr); return gen8_emit_pipe_control(req, flags, scratch_addr);
} }
static void ring_write_tail(struct intel_engine_cs *ring, static void ring_write_tail(struct intel_engine_cs *ring,