drm/amdgpu/mmsch: Correct the definition for mmsch init header
For the header, it is version related, shouldn't use MAX_VCN_INSTANCES. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -30,6 +30,8 @@
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#define MMSCH_VERSION_MINOR 0
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#define MMSCH_VERSION_MINOR 0
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#define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
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#define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
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#define MMSCH_V3_0_VCN_INSTANCES 0x2
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enum mmsch_v3_0_command_type {
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enum mmsch_v3_0_command_type {
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MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
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MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
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MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
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MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
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@ -47,7 +49,7 @@ struct mmsch_v3_0_table_info {
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struct mmsch_v3_0_init_header {
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struct mmsch_v3_0_init_header {
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uint32_t version;
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uint32_t version;
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uint32_t total_size;
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uint32_t total_size;
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struct mmsch_v3_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES];
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struct mmsch_v3_0_table_info inst[MMSCH_V3_0_VCN_INSTANCES];
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};
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};
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struct mmsch_v3_0_cmd_direct_reg_header {
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struct mmsch_v3_0_cmd_direct_reg_header {
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@ -43,6 +43,8 @@
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#define MMSCH_VF_MAILBOX_RESP__OK 0x1
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#define MMSCH_VF_MAILBOX_RESP__OK 0x1
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#define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2
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#define MMSCH_VF_MAILBOX_RESP__INCOMPLETE 0x2
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#define MMSCH_V4_0_VCN_INSTANCES 0x2
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enum mmsch_v4_0_command_type {
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enum mmsch_v4_0_command_type {
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MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
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MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
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MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
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MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
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@ -60,7 +62,7 @@ struct mmsch_v4_0_table_info {
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struct mmsch_v4_0_init_header {
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struct mmsch_v4_0_init_header {
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uint32_t version;
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uint32_t version;
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uint32_t total_size;
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uint32_t total_size;
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struct mmsch_v4_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES];
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struct mmsch_v4_0_table_info inst[MMSCH_V4_0_VCN_INSTANCES];
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struct mmsch_v4_0_table_info jpegdec;
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struct mmsch_v4_0_table_info jpegdec;
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};
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};
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@ -1313,7 +1313,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
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header.version = MMSCH_VERSION;
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header.version = MMSCH_VERSION;
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header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
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header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
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for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
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for (i = 0; i < MMSCH_V3_0_VCN_INSTANCES; i++) {
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header.inst[i].init_status = 0;
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header.inst[i].init_status = 0;
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header.inst[i].table_offset = 0;
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header.inst[i].table_offset = 0;
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header.inst[i].table_size = 0;
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header.inst[i].table_size = 0;
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@ -1239,7 +1239,7 @@ static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
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header.version = MMSCH_VERSION;
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header.version = MMSCH_VERSION;
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header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
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header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
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for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
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for (i = 0; i < MMSCH_V4_0_VCN_INSTANCES; i++) {
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header.inst[i].init_status = 0;
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header.inst[i].init_status = 0;
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header.inst[i].table_offset = 0;
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header.inst[i].table_offset = 0;
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header.inst[i].table_size = 0;
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header.inst[i].table_size = 0;
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