drm/exynos: add gsc ipp driver
This patch adds IPP subsystem-based gsc driver for exynos5 series. GSC is stand for General SCaler and supports the following features: - image scaler/rotator/crop/flip/csc and input/output DMA operations. - image rotation and image effect functions. - writeback and display output operations. - M2M operation to crop, scale, rotation and csc. The below is GSC hardware path: Memory------->GSC------>Memory FIMD--------->GSC------>HDMI FIMD--------->GSC------>Memory Memory------->GSC------>FIMD, Mixer This driver is registered to IPP subsystem framework to be used by user side and user can control the GSC hardware through some interfaces of IPP subsystem framework. Changelog v1 ~ v5: - added comments, code fixups and cleanups. Signed-off-by: Eunchul Kim <chulspro.kim@samsung.com> Signed-off-by: Jinyoung Jeon <jy0.jeon@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kyungmin.park <kyungmin.park@samsung.com>
This commit is contained in:
Eunchul Kim
Inki Dae
parent
bea8a429d9
commit
f264638065
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@ -64,3 +64,8 @@ config DRM_EXYNOS_ROTATOR
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help
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Choose this option if you want to use Exynos Rotator for DRM.
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config DRM_EXYNOS_GSC
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bool "Exynos DRM GSC"
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depends on DRM_EXYNOS_IPP && ARCH_EXYNOS5
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help
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Choose this option if you want to use Exynos GSC for DRM.
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@ -19,5 +19,6 @@ exynosdrm-$(CONFIG_DRM_EXYNOS_G2D) += exynos_drm_g2d.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_IPP) += exynos_drm_ipp.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_FIMC) += exynos_drm_fimc.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_ROTATOR) += exynos_drm_rotator.o
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exynosdrm-$(CONFIG_DRM_EXYNOS_GSC) += exynos_drm_gsc.o
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obj-$(CONFIG_DRM_EXYNOS) += exynosdrm.o
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@ -384,6 +384,12 @@ static int __init exynos_drm_init(void)
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goto out_rotator;
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#endif
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#ifdef CONFIG_DRM_EXYNOS_GSC
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ret = platform_driver_register(&gsc_driver);
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if (ret < 0)
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goto out_gsc;
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#endif
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#ifdef CONFIG_DRM_EXYNOS_IPP
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ret = platform_driver_register(&ipp_driver);
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if (ret < 0)
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@ -412,6 +418,11 @@ out_drm:
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out_ipp:
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#endif
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#ifdef CONFIG_DRM_EXYNOS_GSC
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platform_driver_unregister(&gsc_driver);
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out_gsc:
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#endif
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#ifdef CONFIG_DRM_EXYNOS_ROTATOR
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platform_driver_unregister(&rotator_driver);
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out_rotator:
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@ -462,6 +473,10 @@ static void __exit exynos_drm_exit(void)
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platform_driver_unregister(&ipp_driver);
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#endif
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#ifdef CONFIG_DRM_EXYNOS_GSC
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platform_driver_unregister(&gsc_driver);
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#endif
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#ifdef CONFIG_DRM_EXYNOS_ROTATOR
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platform_driver_unregister(&rotator_driver);
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#endif
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@ -351,5 +351,6 @@ extern struct platform_driver vidi_driver;
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extern struct platform_driver g2d_driver;
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extern struct platform_driver fimc_driver;
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extern struct platform_driver rotator_driver;
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extern struct platform_driver gsc_driver;
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extern struct platform_driver ipp_driver;
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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*
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* Authors:
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* Eunchul Kim <chulspro.kim@samsung.com>
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* Jinyoung Jeon <jy0.jeon@samsung.com>
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* Sangmin Lee <lsmin.lee@samsung.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _EXYNOS_DRM_GSC_H_
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#define _EXYNOS_DRM_GSC_H_
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/*
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* TODO
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* FIMD output interface notifier callback.
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* Mixer output interface notifier callback.
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*/
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#endif /* _EXYNOS_DRM_GSC_H_ */
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@ -0,0 +1,284 @@
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/* linux/drivers/gpu/drm/exynos/regs-gsc.h
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Register definition file for Samsung G-Scaler driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef EXYNOS_REGS_GSC_H_
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#define EXYNOS_REGS_GSC_H_
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/* G-Scaler enable */
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#define GSC_ENABLE 0x00
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#define GSC_ENABLE_PP_UPDATE_TIME_MASK (1 << 9)
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#define GSC_ENABLE_PP_UPDATE_TIME_CURR (0 << 9)
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#define GSC_ENABLE_PP_UPDATE_TIME_EOPAS (1 << 9)
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#define GSC_ENABLE_CLK_GATE_MODE_MASK (1 << 8)
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#define GSC_ENABLE_CLK_GATE_MODE_FREE (1 << 8)
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#define GSC_ENABLE_IPC_MODE_MASK (1 << 7)
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#define GSC_ENABLE_NORM_MODE (0 << 7)
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#define GSC_ENABLE_IPC_MODE (1 << 7)
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#define GSC_ENABLE_PP_UPDATE_MODE_MASK (1 << 6)
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#define GSC_ENABLE_PP_UPDATE_FIRE_MODE (1 << 6)
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#define GSC_ENABLE_IN_PP_UPDATE (1 << 5)
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#define GSC_ENABLE_ON_CLEAR_MASK (1 << 4)
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#define GSC_ENABLE_ON_CLEAR_ONESHOT (1 << 4)
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#define GSC_ENABLE_QOS_ENABLE (1 << 3)
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#define GSC_ENABLE_OP_STATUS (1 << 2)
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#define GSC_ENABLE_SFR_UPDATE (1 << 1)
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#define GSC_ENABLE_ON (1 << 0)
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/* G-Scaler S/W reset */
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#define GSC_SW_RESET 0x04
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#define GSC_SW_RESET_SRESET (1 << 0)
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/* G-Scaler IRQ */
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#define GSC_IRQ 0x08
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#define GSC_IRQ_STATUS_OR_IRQ (1 << 17)
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#define GSC_IRQ_STATUS_OR_FRM_DONE (1 << 16)
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#define GSC_IRQ_OR_MASK (1 << 2)
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#define GSC_IRQ_FRMDONE_MASK (1 << 1)
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#define GSC_IRQ_ENABLE (1 << 0)
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/* G-Scaler input control */
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#define GSC_IN_CON 0x10
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#define GSC_IN_CHROM_STRIDE_SEL_MASK (1 << 20)
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#define GSC_IN_CHROM_STRIDE_SEPAR (1 << 20)
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#define GSC_IN_RB_SWAP_MASK (1 << 19)
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#define GSC_IN_RB_SWAP (1 << 19)
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#define GSC_IN_ROT_MASK (7 << 16)
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#define GSC_IN_ROT_270 (7 << 16)
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#define GSC_IN_ROT_90_YFLIP (6 << 16)
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#define GSC_IN_ROT_90_XFLIP (5 << 16)
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#define GSC_IN_ROT_90 (4 << 16)
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#define GSC_IN_ROT_180 (3 << 16)
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#define GSC_IN_ROT_YFLIP (2 << 16)
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#define GSC_IN_ROT_XFLIP (1 << 16)
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#define GSC_IN_RGB_TYPE_MASK (3 << 14)
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#define GSC_IN_RGB_HD_WIDE (3 << 14)
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#define GSC_IN_RGB_HD_NARROW (2 << 14)
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#define GSC_IN_RGB_SD_WIDE (1 << 14)
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#define GSC_IN_RGB_SD_NARROW (0 << 14)
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#define GSC_IN_YUV422_1P_ORDER_MASK (1 << 13)
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#define GSC_IN_YUV422_1P_ORDER_LSB_Y (0 << 13)
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#define GSC_IN_YUV422_1P_OEDER_LSB_C (1 << 13)
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#define GSC_IN_CHROMA_ORDER_MASK (1 << 12)
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#define GSC_IN_CHROMA_ORDER_CBCR (0 << 12)
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#define GSC_IN_CHROMA_ORDER_CRCB (1 << 12)
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#define GSC_IN_FORMAT_MASK (7 << 8)
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#define GSC_IN_XRGB8888 (0 << 8)
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#define GSC_IN_RGB565 (1 << 8)
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#define GSC_IN_YUV420_2P (2 << 8)
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#define GSC_IN_YUV420_3P (3 << 8)
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#define GSC_IN_YUV422_1P (4 << 8)
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#define GSC_IN_YUV422_2P (5 << 8)
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#define GSC_IN_YUV422_3P (6 << 8)
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#define GSC_IN_TILE_TYPE_MASK (1 << 4)
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#define GSC_IN_TILE_C_16x8 (0 << 4)
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#define GSC_IN_TILE_C_16x16 (1 << 4)
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#define GSC_IN_TILE_MODE (1 << 3)
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#define GSC_IN_LOCAL_SEL_MASK (3 << 1)
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#define GSC_IN_LOCAL_CAM3 (3 << 1)
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#define GSC_IN_LOCAL_FIMD_WB (2 << 1)
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#define GSC_IN_LOCAL_CAM1 (1 << 1)
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#define GSC_IN_LOCAL_CAM0 (0 << 1)
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#define GSC_IN_PATH_MASK (1 << 0)
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#define GSC_IN_PATH_LOCAL (1 << 0)
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#define GSC_IN_PATH_MEMORY (0 << 0)
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/* G-Scaler source image size */
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#define GSC_SRCIMG_SIZE 0x14
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#define GSC_SRCIMG_HEIGHT_MASK (0x1fff << 16)
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#define GSC_SRCIMG_HEIGHT(x) ((x) << 16)
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#define GSC_SRCIMG_WIDTH_MASK (0x3fff << 0)
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#define GSC_SRCIMG_WIDTH(x) ((x) << 0)
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/* G-Scaler source image offset */
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#define GSC_SRCIMG_OFFSET 0x18
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#define GSC_SRCIMG_OFFSET_Y_MASK (0x1fff << 16)
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#define GSC_SRCIMG_OFFSET_Y(x) ((x) << 16)
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#define GSC_SRCIMG_OFFSET_X_MASK (0x1fff << 0)
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#define GSC_SRCIMG_OFFSET_X(x) ((x) << 0)
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/* G-Scaler cropped source image size */
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#define GSC_CROPPED_SIZE 0x1C
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#define GSC_CROPPED_HEIGHT_MASK (0x1fff << 16)
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#define GSC_CROPPED_HEIGHT(x) ((x) << 16)
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#define GSC_CROPPED_WIDTH_MASK (0x1fff << 0)
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#define GSC_CROPPED_WIDTH(x) ((x) << 0)
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/* G-Scaler output control */
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#define GSC_OUT_CON 0x20
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#define GSC_OUT_GLOBAL_ALPHA_MASK (0xff << 24)
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#define GSC_OUT_GLOBAL_ALPHA(x) ((x) << 24)
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#define GSC_OUT_CHROM_STRIDE_SEL_MASK (1 << 13)
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#define GSC_OUT_CHROM_STRIDE_SEPAR (1 << 13)
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#define GSC_OUT_RB_SWAP_MASK (1 << 12)
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#define GSC_OUT_RB_SWAP (1 << 12)
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#define GSC_OUT_RGB_TYPE_MASK (3 << 10)
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#define GSC_OUT_RGB_HD_NARROW (3 << 10)
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#define GSC_OUT_RGB_HD_WIDE (2 << 10)
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#define GSC_OUT_RGB_SD_NARROW (1 << 10)
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#define GSC_OUT_RGB_SD_WIDE (0 << 10)
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#define GSC_OUT_YUV422_1P_ORDER_MASK (1 << 9)
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#define GSC_OUT_YUV422_1P_ORDER_LSB_Y (0 << 9)
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#define GSC_OUT_YUV422_1P_OEDER_LSB_C (1 << 9)
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#define GSC_OUT_CHROMA_ORDER_MASK (1 << 8)
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#define GSC_OUT_CHROMA_ORDER_CBCR (0 << 8)
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#define GSC_OUT_CHROMA_ORDER_CRCB (1 << 8)
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#define GSC_OUT_FORMAT_MASK (7 << 4)
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#define GSC_OUT_XRGB8888 (0 << 4)
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#define GSC_OUT_RGB565 (1 << 4)
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#define GSC_OUT_YUV420_2P (2 << 4)
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#define GSC_OUT_YUV420_3P (3 << 4)
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#define GSC_OUT_YUV422_1P (4 << 4)
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#define GSC_OUT_YUV422_2P (5 << 4)
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#define GSC_OUT_YUV444 (7 << 4)
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#define GSC_OUT_TILE_TYPE_MASK (1 << 2)
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#define GSC_OUT_TILE_C_16x8 (0 << 2)
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#define GSC_OUT_TILE_C_16x16 (1 << 2)
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#define GSC_OUT_TILE_MODE (1 << 1)
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#define GSC_OUT_PATH_MASK (1 << 0)
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#define GSC_OUT_PATH_LOCAL (1 << 0)
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#define GSC_OUT_PATH_MEMORY (0 << 0)
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/* G-Scaler scaled destination image size */
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#define GSC_SCALED_SIZE 0x24
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#define GSC_SCALED_HEIGHT_MASK (0x1fff << 16)
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#define GSC_SCALED_HEIGHT(x) ((x) << 16)
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#define GSC_SCALED_WIDTH_MASK (0x1fff << 0)
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#define GSC_SCALED_WIDTH(x) ((x) << 0)
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/* G-Scaler pre scale ratio */
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#define GSC_PRE_SCALE_RATIO 0x28
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#define GSC_PRESC_SHFACTOR_MASK (7 << 28)
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#define GSC_PRESC_SHFACTOR(x) ((x) << 28)
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#define GSC_PRESC_V_RATIO_MASK (7 << 16)
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#define GSC_PRESC_V_RATIO(x) ((x) << 16)
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#define GSC_PRESC_H_RATIO_MASK (7 << 0)
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#define GSC_PRESC_H_RATIO(x) ((x) << 0)
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/* G-Scaler main scale horizontal ratio */
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#define GSC_MAIN_H_RATIO 0x2C
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#define GSC_MAIN_H_RATIO_MASK (0xfffff << 0)
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#define GSC_MAIN_H_RATIO_VALUE(x) ((x) << 0)
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/* G-Scaler main scale vertical ratio */
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#define GSC_MAIN_V_RATIO 0x30
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#define GSC_MAIN_V_RATIO_MASK (0xfffff << 0)
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#define GSC_MAIN_V_RATIO_VALUE(x) ((x) << 0)
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/* G-Scaler input chrominance stride */
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#define GSC_IN_CHROM_STRIDE 0x3C
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#define GSC_IN_CHROM_STRIDE_MASK (0x3fff << 0)
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#define GSC_IN_CHROM_STRIDE_VALUE(x) ((x) << 0)
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/* G-Scaler destination image size */
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#define GSC_DSTIMG_SIZE 0x40
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#define GSC_DSTIMG_HEIGHT_MASK (0x1fff << 16)
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#define GSC_DSTIMG_HEIGHT(x) ((x) << 16)
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#define GSC_DSTIMG_WIDTH_MASK (0x1fff << 0)
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#define GSC_DSTIMG_WIDTH(x) ((x) << 0)
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/* G-Scaler destination image offset */
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#define GSC_DSTIMG_OFFSET 0x44
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#define GSC_DSTIMG_OFFSET_Y_MASK (0x1fff << 16)
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#define GSC_DSTIMG_OFFSET_Y(x) ((x) << 16)
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#define GSC_DSTIMG_OFFSET_X_MASK (0x1fff << 0)
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#define GSC_DSTIMG_OFFSET_X(x) ((x) << 0)
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/* G-Scaler output chrominance stride */
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#define GSC_OUT_CHROM_STRIDE 0x48
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#define GSC_OUT_CHROM_STRIDE_MASK (0x3fff << 0)
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#define GSC_OUT_CHROM_STRIDE_VALUE(x) ((x) << 0)
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/* G-Scaler input y address mask */
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#define GSC_IN_BASE_ADDR_Y_MASK 0x4C
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/* G-Scaler input y base address */
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#define GSC_IN_BASE_ADDR_Y(n) (0x50 + (n) * 0x4)
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/* G-Scaler input y base current address */
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#define GSC_IN_BASE_ADDR_Y_CUR(n) (0x60 + (n) * 0x4)
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/* G-Scaler input cb address mask */
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#define GSC_IN_BASE_ADDR_CB_MASK 0x7C
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/* G-Scaler input cb base address */
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#define GSC_IN_BASE_ADDR_CB(n) (0x80 + (n) * 0x4)
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/* G-Scaler input cb base current address */
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#define GSC_IN_BASE_ADDR_CB_CUR(n) (0x90 + (n) * 0x4)
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/* G-Scaler input cr address mask */
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#define GSC_IN_BASE_ADDR_CR_MASK 0xAC
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/* G-Scaler input cr base address */
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#define GSC_IN_BASE_ADDR_CR(n) (0xB0 + (n) * 0x4)
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/* G-Scaler input cr base current address */
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#define GSC_IN_BASE_ADDR_CR_CUR(n) (0xC0 + (n) * 0x4)
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/* G-Scaler input address mask */
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#define GSC_IN_CURR_ADDR_INDEX (0xf << 24)
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#define GSC_IN_CURR_GET_INDEX(x) ((x) >> 24)
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#define GSC_IN_BASE_ADDR_PINGPONG(x) ((x) << 16)
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#define GSC_IN_BASE_ADDR_MASK (0xff << 0)
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/* G-Scaler output y address mask */
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#define GSC_OUT_BASE_ADDR_Y_MASK 0x10C
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/* G-Scaler output y base address */
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#define GSC_OUT_BASE_ADDR_Y(n) (0x110 + (n) * 0x4)
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/* G-Scaler output cb address mask */
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#define GSC_OUT_BASE_ADDR_CB_MASK 0x15C
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/* G-Scaler output cb base address */
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#define GSC_OUT_BASE_ADDR_CB(n) (0x160 + (n) * 0x4)
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/* G-Scaler output cr address mask */
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#define GSC_OUT_BASE_ADDR_CR_MASK 0x1AC
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/* G-Scaler output cr base address */
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#define GSC_OUT_BASE_ADDR_CR(n) (0x1B0 + (n) * 0x4)
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/* G-Scaler output address mask */
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#define GSC_OUT_CURR_ADDR_INDEX (0xf << 24)
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#define GSC_OUT_CURR_GET_INDEX(x) ((x) >> 24)
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#define GSC_OUT_BASE_ADDR_PINGPONG(x) ((x) << 16)
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#define GSC_OUT_BASE_ADDR_MASK (0xffff << 0)
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/* G-Scaler horizontal scaling filter */
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#define GSC_HCOEF(n, s, x) (0x300 + (n) * 0x4 + (s) * 0x30 + (x) * 0x300)
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/* G-Scaler vertical scaling filter */
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#define GSC_VCOEF(n, s, x) (0x200 + (n) * 0x4 + (s) * 0x30 + (x) * 0x300)
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/* G-Scaler BUS control */
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#define GSC_BUSCON 0xA78
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#define GSC_BUSCON_INT_TIME_MASK (1 << 8)
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#define GSC_BUSCON_INT_DATA_TRANS (0 << 8)
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#define GSC_BUSCON_INT_AXI_RESPONSE (1 << 8)
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#define GSC_BUSCON_AWCACHE(x) ((x) << 4)
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#define GSC_BUSCON_ARCACHE(x) ((x) << 0)
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/* G-Scaler V position */
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#define GSC_VPOSITION 0xA7C
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#define GSC_VPOS_F(x) ((x) << 0)
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/* G-Scaler clock initial count */
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#define GSC_CLK_INIT_COUNT 0xC00
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#define GSC_CLK_GATE_MODE_INIT_CNT(x) ((x) << 0)
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/* G-Scaler clock snoop count */
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#define GSC_CLK_SNOOP_COUNT 0xC04
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#define GSC_CLK_GATE_MODE_SNOOP_CNT(x) ((x) << 0)
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/* SYSCON. GSCBLK_CFG */
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#define SYSREG_GSCBLK_CFG1 (S3C_VA_SYS + 0x0224)
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#define GSC_BLK_DISP1WB_DEST(x) (x << 10)
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#define GSC_BLK_SW_RESET_WB_DEST(x) (1 << (18 + x))
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#define GSC_BLK_PXLASYNC_LO_MASK_WB(x) (0 << (14 + x))
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#define GSC_BLK_GSCL_WB_IN_SRC_SEL(x) (1 << (2 * x))
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#define SYSREG_GSCBLK_CFG2 (S3C_VA_SYS + 0x2000)
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#define PXLASYNC_LO_MASK_CAMIF_GSCL(x) (1 << (x))
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|
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#endif /* EXYNOS_REGS_GSC_H_ */
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Loading…
Reference in New Issue