xtensa: s6000 dma engine support
There are four slightly different dma engines on the s6000 family. One for memory-memory transfers, the other three for memory-device. This patch implements a platform-specific kernel-API to control these engines. It is needed for the network, video, audio peripherals on s6000. Signed-off-by: Oskar Schirmer <os@emlix.com> Signed-off-by: Daniel Glockner <dg@emlix.com> Signed-off-by: Fabian Godehardt <fg@emlix.com> Cc: Daniel Glockner <dg@emlix.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Chris Zankel <chris@zankel.net>
This commit is contained in:
Oskar Schirmer
Chris Zankel
parent
1beee21030
commit
f24e552c2d
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@ -1,4 +1,4 @@
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# s6000 Makefile
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obj-y += irq.o gpio.o
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obj-y += irq.o gpio.o dmac.o
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obj-$(CONFIG_XTENSA_CALIBRATE_CCOUNT) += delay.o
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@ -0,0 +1,173 @@
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/*
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* Authors: Oskar Schirmer <os@emlix.com>
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* Daniel Gloeckner <dg@emlix.com>
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* (c) 2008 emlix GmbH http://www.emlix.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <asm/cacheflush.h>
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#include <variant/dmac.h>
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/* DMA engine lookup */
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struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
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/* DMA control, per engine */
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void s6dmac_put_fifo_cache(u32 dmac, int chan, u32 src, u32 dst, u32 size)
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{
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if (xtensa_need_flush_dma_source(src)) {
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u32 base = src;
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u32 span = size;
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u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
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if (chunk && (size > chunk)) {
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s32 skip =
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readl(DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
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u32 gaps = (size+chunk-1)/chunk - 1;
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if (skip >= 0) {
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span += gaps * skip;
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} else if (-skip > chunk) {
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s32 decr = gaps * (chunk + skip);
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base += decr;
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span = chunk - decr;
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} else {
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span = max(span + gaps * skip,
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(chunk + skip) * gaps - skip);
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}
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}
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flush_dcache_unaligned(base, span);
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}
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if (xtensa_need_invalidate_dma_destination(dst)) {
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u32 base = dst;
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u32 span = size;
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u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
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if (chunk && (size > chunk)) {
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s32 skip =
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readl(DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
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u32 gaps = (size+chunk-1)/chunk - 1;
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if (skip >= 0) {
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span += gaps * skip;
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} else if (-skip > chunk) {
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s32 decr = gaps * (chunk + skip);
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base += decr;
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span = chunk - decr;
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} else {
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span = max(span + gaps * skip,
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(chunk + skip) * gaps - skip);
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}
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}
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invalidate_dcache_unaligned(base, span);
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}
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s6dmac_put_fifo(dmac, chan, src, dst, size);
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}
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void s6dmac_disable_error_irqs(u32 dmac, u32 mask)
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{
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unsigned long flags;
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spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
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spin_lock_irqsave(spinl, flags);
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_s6dmac_disable_error_irqs(dmac, mask);
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spin_unlock_irqrestore(spinl, flags);
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}
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u32 s6dmac_int_sources(u32 dmac, u32 channel)
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{
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u32 mask, ret, tmp;
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mask = 1 << channel;
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tmp = readl(dmac + S6_DMA_TERMCNTIRQSTAT);
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tmp &= mask;
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writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR);
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ret = tmp >> channel;
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tmp = readl(dmac + S6_DMA_PENDCNTIRQSTAT);
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tmp &= mask;
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writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR);
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ret |= (tmp >> channel) << 1;
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tmp = readl(dmac + S6_DMA_LOWWMRKIRQSTAT);
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tmp &= mask;
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writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR);
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ret |= (tmp >> channel) << 2;
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tmp = readl(dmac + S6_DMA_INTRAW0);
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tmp &= (mask << S6_DMA_INT0_OVER) | (mask << S6_DMA_INT0_UNDER);
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writel(tmp, dmac + S6_DMA_INTCLEAR0);
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if (tmp & (mask << S6_DMA_INT0_UNDER))
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ret |= 1 << 3;
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if (tmp & (mask << S6_DMA_INT0_OVER))
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ret |= 1 << 4;
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tmp = readl(dmac + S6_DMA_MASTERERRINFO);
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mask <<= S6_DMA_INT1_CHANNEL;
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if (((tmp >> S6_DMA_MASTERERR_CHAN(0)) & S6_DMA_MASTERERR_CHAN_MASK)
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== channel)
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mask |= 1 << S6_DMA_INT1_MASTER;
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if (((tmp >> S6_DMA_MASTERERR_CHAN(1)) & S6_DMA_MASTERERR_CHAN_MASK)
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== channel)
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mask |= 1 << (S6_DMA_INT1_MASTER + 1);
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if (((tmp >> S6_DMA_MASTERERR_CHAN(2)) & S6_DMA_MASTERERR_CHAN_MASK)
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== channel)
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mask |= 1 << (S6_DMA_INT1_MASTER + 2);
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tmp = readl(dmac + S6_DMA_INTRAW1) & mask;
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writel(tmp, dmac + S6_DMA_INTCLEAR1);
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ret |= ((tmp >> channel) & 1) << 5;
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ret |= ((tmp >> S6_DMA_INT1_MASTER) & S6_DMA_INT1_MASTER_MASK) << 6;
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return ret;
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}
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void s6dmac_release_chan(u32 dmac, int chan)
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{
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if (chan >= 0)
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s6dmac_disable_chan(dmac, chan);
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}
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/* global init */
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static inline void __init dmac_init(u32 dmac, u8 chan_nb)
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{
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s6dmac_ctrl[S6_DMAC_INDEX(dmac)].dmac = dmac;
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spin_lock_init(&s6dmac_ctrl[S6_DMAC_INDEX(dmac)].lock);
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s6dmac_ctrl[S6_DMAC_INDEX(dmac)].chan_nb = chan_nb;
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writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER,
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dmac + S6_DMA_INTCLEAR1);
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}
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static inline void __init dmac_master(u32 dmac,
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u32 m0start, u32 m0end, u32 m1start, u32 m1end)
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{
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writel(m0start, dmac + S6_DMA_MASTER0START);
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writel(m0end - 1, dmac + S6_DMA_MASTER0END);
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writel(m1start, dmac + S6_DMA_MASTER1START);
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writel(m1end - 1, dmac + S6_DMA_MASTER1END);
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}
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static void __init s6_dmac_init(void)
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{
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dmac_init(S6_REG_LMSDMA, S6_LMSDMA_NB);
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dmac_master(S6_REG_LMSDMA,
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S6_MEM_DDR, S6_MEM_PCIE_APER, S6_MEM_EFI, S6_MEM_GMAC);
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dmac_init(S6_REG_NIDMA, S6_NIDMA_NB);
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dmac_init(S6_REG_DPDMA, S6_DPDMA_NB);
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dmac_master(S6_REG_DPDMA,
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S6_MEM_DDR, S6_MEM_PCIE_APER, S6_REG_DP, S6_REG_DPDMA);
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dmac_init(S6_REG_HIFDMA, S6_HIFDMA_NB);
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dmac_master(S6_REG_HIFDMA,
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S6_MEM_GMAC, S6_MEM_PCIE_CFG, S6_MEM_PCIE_APER, S6_MEM_AUX);
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}
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arch_initcall(s6_dmac_init);
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@ -0,0 +1,387 @@
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/*
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* include/asm-xtensa/variant-s6000/dmac.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Tensilica Inc.
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* Copyright (C) 2008 Emlix GmbH <info@emlix.com>
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* Authors: Fabian Godehardt <fg@emlix.com>
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* Oskar Schirmer <os@emlix.com>
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* Daniel Gloeckner <dg@emlix.com>
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*/
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#ifndef __ASM_XTENSA_S6000_DMAC_H
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#define __ASM_XTENSA_S6000_DMAC_H
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#include <linux/io.h>
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#include <variant/hardware.h>
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/* DMA global */
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#define S6_DMA_INTSTAT0 0x000
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#define S6_DMA_INTSTAT1 0x004
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#define S6_DMA_INTENABLE0 0x008
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#define S6_DMA_INTENABLE1 0x00C
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#define S6_DMA_INTRAW0 0x010
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#define S6_DMA_INTRAW1 0x014
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#define S6_DMA_INTCLEAR0 0x018
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#define S6_DMA_INTCLEAR1 0x01C
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#define S6_DMA_INTSET0 0x020
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#define S6_DMA_INTSET1 0x024
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#define S6_DMA_INT0_UNDER 0
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#define S6_DMA_INT0_OVER 16
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#define S6_DMA_INT1_CHANNEL 0
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#define S6_DMA_INT1_MASTER 16
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#define S6_DMA_INT1_MASTER_MASK 7
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#define S6_DMA_TERMCNTIRQSTAT 0x028
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#define S6_DMA_TERMCNTIRQCLR 0x02C
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#define S6_DMA_TERMCNTIRQSET 0x030
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#define S6_DMA_PENDCNTIRQSTAT 0x034
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#define S6_DMA_PENDCNTIRQCLR 0x038
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#define S6_DMA_PENDCNTIRQSET 0x03C
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#define S6_DMA_LOWWMRKIRQSTAT 0x040
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#define S6_DMA_LOWWMRKIRQCLR 0x044
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#define S6_DMA_LOWWMRKIRQSET 0x048
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#define S6_DMA_MASTERERRINFO 0x04C
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#define S6_DMA_MASTERERR_CHAN(n) (4*(n))
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#define S6_DMA_MASTERERR_CHAN_MASK 0xF
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#define S6_DMA_DESCRFIFO0 0x050
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#define S6_DMA_DESCRFIFO1 0x054
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#define S6_DMA_DESCRFIFO2 0x058
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#define S6_DMA_DESCRFIFO2_AUTODISABLE 24
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#define S6_DMA_DESCRFIFO3 0x05C
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#define S6_DMA_MASTER0START 0x060
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#define S6_DMA_MASTER0END 0x064
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#define S6_DMA_MASTER1START 0x068
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#define S6_DMA_MASTER1END 0x06C
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#define S6_DMA_NEXTFREE 0x070
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#define S6_DMA_NEXTFREE_CHAN 0
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#define S6_DMA_NEXTFREE_CHAN_MASK 0x1F
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#define S6_DMA_NEXTFREE_ENA 16
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#define S6_DMA_NEXTFREE_ENA_MASK ((1 << 16) - 1)
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#define S6_DMA_DPORTCTRLGRP(p) ((p) * 4 + 0x074)
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#define S6_DMA_DPORTCTRLGRP_FRAMEREP 0
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#define S6_DMA_DPORTCTRLGRP_NRCHANS 1
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#define S6_DMA_DPORTCTRLGRP_NRCHANS_1 0
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#define S6_DMA_DPORTCTRLGRP_NRCHANS_3 1
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#define S6_DMA_DPORTCTRLGRP_NRCHANS_4 2
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#define S6_DMA_DPORTCTRLGRP_NRCHANS_2 3
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#define S6_DMA_DPORTCTRLGRP_ENA 31
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/* DMA per channel */
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#define DMA_CHNL(dmac, n) ((dmac) + 0x1000 + (n) * 0x100)
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#define DMA_INDEX_CHNL(addr) (((addr) >> 8) & 0xF)
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#define DMA_MASK_DMAC(addr) ((addr) & 0xFFFF0000)
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#define S6_DMA_CHNCTRL 0x000
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#define S6_DMA_CHNCTRL_ENABLE 0
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#define S6_DMA_CHNCTRL_PAUSE 1
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#define S6_DMA_CHNCTRL_PRIO 2
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#define S6_DMA_CHNCTRL_PRIO_MASK 3
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#define S6_DMA_CHNCTRL_PERIPHXFER 4
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#define S6_DMA_CHNCTRL_PERIPHENA 5
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#define S6_DMA_CHNCTRL_SRCINC 6
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#define S6_DMA_CHNCTRL_DSTINC 7
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#define S6_DMA_CHNCTRL_BURSTLOG 8
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#define S6_DMA_CHNCTRL_BURSTLOG_MASK 7
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#define S6_DMA_CHNCTRL_DESCFIFODEPTH 12
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#define S6_DMA_CHNCTRL_DESCFIFODEPTH_MASK 0x1F
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#define S6_DMA_CHNCTRL_DESCFIFOFULL 17
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#define S6_DMA_CHNCTRL_BWCONSEL 18
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#define S6_DMA_CHNCTRL_BWCONENA 19
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#define S6_DMA_CHNCTRL_PENDGCNTSTAT 20
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#define S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK 0x3F
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#define S6_DMA_CHNCTRL_LOWWMARK 26
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#define S6_DMA_CHNCTRL_LOWWMARK_MASK 0xF
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#define S6_DMA_CHNCTRL_TSTAMP 30
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#define S6_DMA_TERMCNTNB 0x004
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#define S6_DMA_TERMCNTNB_MASK 0xFFFF
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#define S6_DMA_TERMCNTTMO 0x008
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#define S6_DMA_TERMCNTSTAT 0x00C
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#define S6_DMA_TERMCNTSTAT_MASK 0xFF
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#define S6_DMA_CMONCHUNK 0x010
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#define S6_DMA_SRCSKIP 0x014
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#define S6_DMA_DSTSKIP 0x018
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#define S6_DMA_CUR_SRC 0x024
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#define S6_DMA_CUR_DST 0x028
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#define S6_DMA_TIMESTAMP 0x030
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/* DMA channel lists */
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#define S6_DPDMA_CHAN(stream, channel) (4 * (stream) + (channel))
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#define S6_DPDMA_NB 16
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#define S6_HIFDMA_GMACTX 0
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#define S6_HIFDMA_GMACRX 1
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#define S6_HIFDMA_I2S0 2
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#define S6_HIFDMA_I2S1 3
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#define S6_HIFDMA_EGIB 4
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#define S6_HIFDMA_PCITX 5
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#define S6_HIFDMA_PCIRX 6
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#define S6_HIFDMA_NB 7
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#define S6_NIDMA_NB 4
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#define S6_LMSDMA_NB 12
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/* controller access */
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#define S6_DMAC_NB 4
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#define S6_DMAC_INDEX(dmac) (((unsigned)(dmac) >> 18) % S6_DMAC_NB)
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struct s6dmac_ctrl {
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u32 dmac;
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spinlock_t lock;
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u8 chan_nb;
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};
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extern struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
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/* DMA control, per channel */
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static inline int s6dmac_fifo_full(u32 dmac, int chan)
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{
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return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
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& (1 << S6_DMA_CHNCTRL_DESCFIFOFULL)) && 1;
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}
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static inline int s6dmac_termcnt_irq(u32 dmac, int chan)
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{
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u32 m = 1 << chan;
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int r = (readl(dmac + S6_DMA_TERMCNTIRQSTAT) & m) && 1;
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if (r)
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writel(m, dmac + S6_DMA_TERMCNTIRQCLR);
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return r;
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}
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static inline int s6dmac_pendcnt_irq(u32 dmac, int chan)
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{
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u32 m = 1 << chan;
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int r = (readl(dmac + S6_DMA_PENDCNTIRQSTAT) & m) && 1;
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if (r)
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writel(m, dmac + S6_DMA_PENDCNTIRQCLR);
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return r;
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}
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static inline int s6dmac_lowwmark_irq(u32 dmac, int chan)
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{
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int r = (readl(dmac + S6_DMA_LOWWMRKIRQSTAT) & (1 << chan)) ? 1 : 0;
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if (r)
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writel(1 << chan, dmac + S6_DMA_LOWWMRKIRQCLR);
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return r;
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}
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static inline u32 s6dmac_pending_count(u32 dmac, int chan)
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{
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return (readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
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>> S6_DMA_CHNCTRL_PENDGCNTSTAT)
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& S6_DMA_CHNCTRL_PENDGCNTSTAT_MASK;
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}
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static inline void s6dmac_set_terminal_count(u32 dmac, int chan, u32 n)
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{
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n &= S6_DMA_TERMCNTNB_MASK;
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n |= readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB)
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& ~S6_DMA_TERMCNTNB_MASK;
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writel(n, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
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}
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static inline u32 s6dmac_get_terminal_count(u32 dmac, int chan)
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{
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return (readl(DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB))
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& S6_DMA_TERMCNTNB_MASK;
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}
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static inline u32 s6dmac_timestamp(u32 dmac, int chan)
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{
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return readl(DMA_CHNL(dmac, chan) + S6_DMA_TIMESTAMP);
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}
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static inline u32 s6dmac_cur_src(u32 dmac, int chan)
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{
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return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_SRC);
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}
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static inline u32 s6dmac_cur_dst(u32 dmac, int chan)
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{
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return readl(DMA_CHNL(dmac, chan) + S6_DMA_CUR_DST);
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||||
}
|
||||
|
||||
static inline void s6dmac_disable_chan(u32 dmac, int chan)
|
||||
{
|
||||
u32 ctrl;
|
||||
writel(readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL)
|
||||
& ~(1 << S6_DMA_CHNCTRL_ENABLE),
|
||||
DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
|
||||
do
|
||||
ctrl = readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
|
||||
while (ctrl & (1 << S6_DMA_CHNCTRL_ENABLE));
|
||||
}
|
||||
|
||||
static inline void s6dmac_set_stride_skip(u32 dmac, int chan,
|
||||
int comchunk, /* 0: disable scatter/gather */
|
||||
int srcskip, int dstskip)
|
||||
{
|
||||
writel(comchunk, DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
|
||||
writel(srcskip, DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
|
||||
writel(dstskip, DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
|
||||
}
|
||||
|
||||
static inline void s6dmac_enable_chan(u32 dmac, int chan,
|
||||
int prio, /* 0 (highest) .. 3 (lowest) */
|
||||
int periphxfer, /* <0: disable p.req.line, 0..1: mode */
|
||||
int srcinc, int dstinc, /* 0: dont increment src/dst address */
|
||||
int comchunk, /* 0: disable scatter/gather */
|
||||
int srcskip, int dstskip,
|
||||
int burstsize, /* 4 for I2S, 7 for everything else */
|
||||
int bandwidthconserve, /* <0: disable, 0..1: select */
|
||||
int lowwmark, /* 0..15 */
|
||||
int timestamp, /* 0: disable timestamp */
|
||||
int enable) /* 0: disable for now */
|
||||
{
|
||||
writel(1, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTNB);
|
||||
writel(0, DMA_CHNL(dmac, chan) + S6_DMA_TERMCNTTMO);
|
||||
writel(lowwmark << S6_DMA_CHNCTRL_LOWWMARK,
|
||||
DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
|
||||
s6dmac_set_stride_skip(dmac, chan, comchunk, srcskip, dstskip);
|
||||
writel(((enable ? 1 : 0) << S6_DMA_CHNCTRL_ENABLE) |
|
||||
(prio << S6_DMA_CHNCTRL_PRIO) |
|
||||
(((periphxfer > 0) ? 1 : 0) << S6_DMA_CHNCTRL_PERIPHXFER) |
|
||||
(((periphxfer < 0) ? 0 : 1) << S6_DMA_CHNCTRL_PERIPHENA) |
|
||||
((srcinc ? 1 : 0) << S6_DMA_CHNCTRL_SRCINC) |
|
||||
((dstinc ? 1 : 0) << S6_DMA_CHNCTRL_DSTINC) |
|
||||
(burstsize << S6_DMA_CHNCTRL_BURSTLOG) |
|
||||
(((bandwidthconserve > 0) ? 1 : 0) << S6_DMA_CHNCTRL_BWCONSEL) |
|
||||
(((bandwidthconserve < 0) ? 0 : 1) << S6_DMA_CHNCTRL_BWCONENA) |
|
||||
(lowwmark << S6_DMA_CHNCTRL_LOWWMARK) |
|
||||
((timestamp ? 1 : 0) << S6_DMA_CHNCTRL_TSTAMP),
|
||||
DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL);
|
||||
}
|
||||
|
||||
|
||||
/* DMA control, per engine */
|
||||
|
||||
static inline unsigned _dmac_addr_index(u32 dmac)
|
||||
{
|
||||
unsigned i = S6_DMAC_INDEX(dmac);
|
||||
if (s6dmac_ctrl[i].dmac != dmac)
|
||||
BUG();
|
||||
return i;
|
||||
}
|
||||
|
||||
static inline void _s6dmac_disable_error_irqs(u32 dmac, u32 mask)
|
||||
{
|
||||
writel(mask, dmac + S6_DMA_TERMCNTIRQCLR);
|
||||
writel(mask, dmac + S6_DMA_PENDCNTIRQCLR);
|
||||
writel(mask, dmac + S6_DMA_LOWWMRKIRQCLR);
|
||||
writel(readl(dmac + S6_DMA_INTENABLE0)
|
||||
& ~((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER)),
|
||||
dmac + S6_DMA_INTENABLE0);
|
||||
writel(readl(dmac + S6_DMA_INTENABLE1) & ~(mask << S6_DMA_INT1_CHANNEL),
|
||||
dmac + S6_DMA_INTENABLE1);
|
||||
writel((mask << S6_DMA_INT0_UNDER) | (mask << S6_DMA_INT0_OVER),
|
||||
dmac + S6_DMA_INTCLEAR0);
|
||||
writel(mask << S6_DMA_INT1_CHANNEL, dmac + S6_DMA_INTCLEAR1);
|
||||
}
|
||||
|
||||
/*
|
||||
* request channel from specified engine
|
||||
* with chan<0, accept any channel
|
||||
* further parameters see s6dmac_enable_chan
|
||||
* returns < 0 upon error, channel nb otherwise
|
||||
*/
|
||||
static inline int s6dmac_request_chan(u32 dmac, int chan,
|
||||
int prio,
|
||||
int periphxfer,
|
||||
int srcinc, int dstinc,
|
||||
int comchunk,
|
||||
int srcskip, int dstskip,
|
||||
int burstsize,
|
||||
int bandwidthconserve,
|
||||
int lowwmark,
|
||||
int timestamp,
|
||||
int enable)
|
||||
{
|
||||
int r = chan;
|
||||
unsigned long flags;
|
||||
spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
|
||||
spin_lock_irqsave(spinl, flags);
|
||||
if (r < 0) {
|
||||
r = (readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_CHAN)
|
||||
& S6_DMA_NEXTFREE_CHAN_MASK;
|
||||
}
|
||||
if (r >= s6dmac_ctrl[_dmac_addr_index(dmac)].chan_nb) {
|
||||
if (chan < 0)
|
||||
r = -EBUSY;
|
||||
else
|
||||
r = -ENXIO;
|
||||
} else if (((readl(dmac + S6_DMA_NEXTFREE) >> S6_DMA_NEXTFREE_ENA)
|
||||
>> r) & 1) {
|
||||
r = -EBUSY;
|
||||
} else {
|
||||
s6dmac_enable_chan(dmac, r, prio, periphxfer,
|
||||
srcinc, dstinc, comchunk, srcskip, dstskip, burstsize,
|
||||
bandwidthconserve, lowwmark, timestamp, enable);
|
||||
}
|
||||
spin_unlock_irqrestore(spinl, flags);
|
||||
return r;
|
||||
}
|
||||
|
||||
static inline void s6dmac_put_fifo(u32 dmac, int chan,
|
||||
u32 src, u32 dst, u32 size)
|
||||
{
|
||||
unsigned long flags;
|
||||
spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
|
||||
spin_lock_irqsave(spinl, flags);
|
||||
writel(src, dmac + S6_DMA_DESCRFIFO0);
|
||||
writel(dst, dmac + S6_DMA_DESCRFIFO1);
|
||||
writel(size, dmac + S6_DMA_DESCRFIFO2);
|
||||
writel(chan, dmac + S6_DMA_DESCRFIFO3);
|
||||
spin_unlock_irqrestore(spinl, flags);
|
||||
}
|
||||
|
||||
static inline u32 s6dmac_channel_enabled(u32 dmac, int chan)
|
||||
{
|
||||
return readl(DMA_CHNL(dmac, chan) + S6_DMA_CHNCTRL) &
|
||||
(1 << S6_DMA_CHNCTRL_ENABLE);
|
||||
}
|
||||
|
||||
/*
|
||||
* group 1-4 data port channels
|
||||
* with port=0..3, nrch=1-4 channels,
|
||||
* frrep=0/1 (dis- or enable frame repeat)
|
||||
*/
|
||||
static inline void s6dmac_dp_setup_group(u32 dmac, int port,
|
||||
int nrch, int frrep)
|
||||
{
|
||||
const static u8 mask[4] = {0, 3, 1, 2};
|
||||
BUG_ON(dmac != S6_REG_DPDMA);
|
||||
if ((port < 0) || (port > 3) || (nrch < 1) || (nrch > 4))
|
||||
return;
|
||||
writel((mask[nrch - 1] << S6_DMA_DPORTCTRLGRP_NRCHANS)
|
||||
| ((frrep ? 1 : 0) << S6_DMA_DPORTCTRLGRP_FRAMEREP),
|
||||
dmac + S6_DMA_DPORTCTRLGRP(port));
|
||||
}
|
||||
|
||||
static inline void s6dmac_dp_switch_group(u32 dmac, int port, int enable)
|
||||
{
|
||||
u32 tmp;
|
||||
BUG_ON(dmac != S6_REG_DPDMA);
|
||||
tmp = readl(dmac + S6_DMA_DPORTCTRLGRP(port));
|
||||
if (enable)
|
||||
tmp |= (1 << S6_DMA_DPORTCTRLGRP_ENA);
|
||||
else
|
||||
tmp &= ~(1 << S6_DMA_DPORTCTRLGRP_ENA);
|
||||
writel(tmp, dmac + S6_DMA_DPORTCTRLGRP(port));
|
||||
}
|
||||
|
||||
extern void s6dmac_put_fifo_cache(u32 dmac, int chan,
|
||||
u32 src, u32 dst, u32 size);
|
||||
extern void s6dmac_disable_error_irqs(u32 dmac, u32 mask);
|
||||
extern u32 s6dmac_int_sources(u32 dmac, u32 channel);
|
||||
extern void s6dmac_release_chan(u32 dmac, int chan);
|
||||
|
||||
#endif /* __ASM_XTENSA_S6000_DMAC_H */
|
||||
Loading…
Reference in New Issue