drm/amd/display: add asics info for SI parts

[Why]
Asic info for SI parts need to be preliminarly added

[How]
Asics info retrieved from si_id.h in https://github.com/GPUOpen-Tools/CodeXL

Tree path:
./CodeXL/Components/ShaderAnalyzer/AMDTBackEnd/Include/Common/asic_reg/si_id.h

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
This commit is contained in:
Mauro Rossi 2020-07-11 21:28:48 +02:00 committed by Alex Deucher
parent 6863660d72
commit f233c09842
2 changed files with 43 additions and 0 deletions

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@ -30,6 +30,34 @@
* ASIC internal revision ID * ASIC internal revision ID
*/ */
/* DCE60 (based on si_id.h in GPUOpen-Tools CodeXL) */
#define SI_TAHITI_P_A0 0x01
#define SI_TAHITI_P_B0 0x05
#define SI_TAHITI_P_B1 0x06
#define SI_PITCAIRN_PM_A0 0x14
#define SI_PITCAIRN_PM_A1 0x15
#define SI_CAPEVERDE_M_A0 0x28
#define SI_CAPEVERDE_M_A1 0x29
#define SI_OLAND_M_A0 0x3C
#define SI_HAINAN_V_A0 0x46
#define SI_UNKNOWN 0xFF
#define ASIC_REV_IS_TAHITI_P(rev) \
((rev >= SI_TAHITI_P_A0) && (rev < SI_PITCAIRN_PM_A0))
#define ASIC_REV_IS_PITCAIRN_PM(rev) \
((rev >= SI_PITCAIRN_PM_A0) && (rev < SI_CAPEVERDE_M_A0))
#define ASIC_REV_IS_CAPEVERDE_M(rev) \
((rev >= SI_CAPEVERDE_M_A0) && (rev < SI_OLAND_M_A0))
#define ASIC_REV_IS_OLAND_M(rev) \
((rev >= SI_OLAND_M_A0) && (rev < SI_HAINAN_V_A0))
#define ASIC_REV_IS_HAINAN_V(rev) \
((rev >= SI_HAINAN_V_A0) && (rev < SI_UNKNOWN))
/* DCE80 (based on ci_id.h in Perforce) */ /* DCE80 (based on ci_id.h in Perforce) */
#define CI_BONAIRE_M_A0 0x14 #define CI_BONAIRE_M_A0 0x14
#define CI_BONAIRE_M_A1 0x15 #define CI_BONAIRE_M_A1 0x15
@ -181,6 +209,17 @@ enum {
/* /*
* ASIC chip ID * ASIC chip ID
*/ */
/* DCE60 */
#define DEVICE_ID_SI_TAHITI_P_6780 0x6780
#define DEVICE_ID_SI_PITCAIRN_PM_6800 0x6800
#define DEVICE_ID_SI_PITCAIRN_PM_6808 0x6808
#define DEVICE_ID_SI_CAPEVERDE_M_6820 0x6820
#define DEVICE_ID_SI_CAPEVERDE_M_6828 0x6828
#define DEVICE_ID_SI_OLAND_M_6600 0x6600
#define DEVICE_ID_SI_OLAND_M_6608 0x6608
#define DEVICE_ID_SI_HAINAN_V_6660 0x6660
/* DCE80 */ /* DCE80 */
#define DEVICE_ID_KALINDI_9834 0x9834 #define DEVICE_ID_KALINDI_9834 0x9834
#define DEVICE_ID_TEMASH_9839 0x9839 #define DEVICE_ID_TEMASH_9839 0x9839
@ -190,6 +229,7 @@ enum {
#define DEVICE_ID_RENOIR_1636 0x1636 #define DEVICE_ID_RENOIR_1636 0x1636
/* Asic Family IDs for different asic family. */ /* Asic Family IDs for different asic family. */
#define FAMILY_SI 110 /* Southern Islands: Tahiti (P), Pitcairn (PM), Cape Verde (M), Oland (M), Hainan (V) */
#define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */ #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
#define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */ #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
#define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */

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@ -34,6 +34,9 @@ struct dc_bios;
enum dce_version { enum dce_version {
DCE_VERSION_UNKNOWN = (-1), DCE_VERSION_UNKNOWN = (-1),
DCE_VERSION_6_0,
DCE_VERSION_6_1,
DCE_VERSION_6_4,
DCE_VERSION_8_0, DCE_VERSION_8_0,
DCE_VERSION_8_1, DCE_VERSION_8_1,
DCE_VERSION_8_3, DCE_VERSION_8_3,