drm/nouveau: Clean up trailing whitespace and C99-style comments.
Fix 'ERROR: trailing whitespace', Fix 'ERROR: do not use C99 // comments' Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Emil Velikov
Ben Skeggs
parent
71298e2f0b
commit
f212949ced
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@ -861,7 +861,7 @@ static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
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#ifdef CONFIG_X86
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primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
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#endif
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remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
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return 0;
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}
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@ -507,7 +507,7 @@ int nv04_graph_init(struct drm_device *dev)
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nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
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nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x1231c000);
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/*1231C000 blob, 001 haiku*/
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//*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
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/*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
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nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x72111100);
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/*0x72111100 blob , 01 haiku*/
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/*nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
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@ -924,7 +924,7 @@ nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx)
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dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */
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} else {
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dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */
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}
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}
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dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */
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if (dev_priv->chipset != 0x50)
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dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */
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@ -452,28 +452,30 @@ nvc0_graph_init_gpc_0(struct drm_device *dev)
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
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int gpc;
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// TP ROP UNKVAL(magic_not_rop_nr)
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// 450: 4/0/0/0 2 3
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// 460: 3/4/0/0 4 1
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// 465: 3/4/4/0 4 7
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// 470: 3/3/4/4 5 5
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// 480: 3/4/4/4 6 6
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// magicgpc918
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// 450: 00200000 00000000001000000000000000000000
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// 460: 00124925 00000000000100100100100100100101
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// 465: 000ba2e9 00000000000010111010001011101001
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// 470: 00092493 00000000000010010010010010010011
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// 480: 00088889 00000000000010001000100010001001
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/*
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* TP ROP UNKVAL(magic_not_rop_nr)
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* 450: 4/0/0/0 2 3
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* 460: 3/4/0/0 4 1
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* 465: 3/4/4/0 4 7
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* 470: 3/3/4/4 5 5
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* 480: 3/4/4/4 6 6
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* magicgpc918
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* 450: 00200000 00000000001000000000000000000000
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* 460: 00124925 00000000000100100100100100100101
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* 465: 000ba2e9 00000000000010111010001011101001
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* 470: 00092493 00000000000010010010010010010011
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* 480: 00088889 00000000000010001000100010001001
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* filled values up to tp_total, remainder 0
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* 450: 00003210 00000000 00000000 00000000
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* 460: 02321100 00000000 00000000 00000000
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* 465: 22111000 00000233 00000000 00000000
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* 470: 11110000 00233222 00000000 00000000
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* 480: 11110000 03332222 00000000 00000000
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*/
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/* filled values up to tp_total, remainder 0 */
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// 450: 00003210 00000000 00000000 00000000
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// 460: 02321100 00000000 00000000 00000000
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// 465: 22111000 00000233 00000000 00000000
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// 470: 11110000 00233222 00000000 00000000
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// 480: 11110000 03332222 00000000 00000000
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nv_wr32(dev, GPC_BCAST(0x0980), priv->magicgpc980[0]);
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nv_wr32(dev, GPC_BCAST(0x0984), priv->magicgpc980[1]);
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nv_wr32(dev, GPC_BCAST(0x0988), priv->magicgpc980[2]);
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@ -676,9 +678,9 @@ nvc0_graph_init(struct drm_device *dev)
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nvc0_graph_init_obj418880(dev);
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nvc0_graph_init_regs(dev);
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//nvc0_graph_init_unitplemented_magics(dev);
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/*nvc0_graph_init_unitplemented_magics(dev);*/
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nvc0_graph_init_gpc_0(dev);
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//nvc0_graph_init_unitplemented_c242(dev);
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/*nvc0_graph_init_unitplemented_c242(dev);*/
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nv_wr32(dev, 0x400500, 0x00010001);
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nv_wr32(dev, 0x400100, 0xffffffff);
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@ -52,9 +52,9 @@ struct nvc0_graph_priv {
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struct nvc0_graph_chan {
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struct nouveau_gpuobj *grctx;
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struct nouveau_gpuobj *unk408004; // 0x418810 too
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struct nouveau_gpuobj *unk40800c; // 0x419004 too
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struct nouveau_gpuobj *unk418810; // 0x419848 too
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struct nouveau_gpuobj *unk408004; /* 0x418810 too */
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struct nouveau_gpuobj *unk40800c; /* 0x419004 too */
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struct nouveau_gpuobj *unk418810; /* 0x419848 too */
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struct nouveau_gpuobj *mmio;
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int mmio_nr;
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};
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@ -1623,7 +1623,7 @@ nvc0_grctx_generate_rop(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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// ROPC_BROADCAST
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/* ROPC_BROADCAST */
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nv_wr32(dev, 0x408800, 0x02802a3c);
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nv_wr32(dev, 0x408804, 0x00000040);
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nv_wr32(dev, 0x408808, 0x0003e00d);
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@ -1647,7 +1647,7 @@ nvc0_grctx_generate_gpc(struct drm_device *dev)
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{
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int i;
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// GPC_BROADCAST
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/* GPC_BROADCAST */
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nv_wr32(dev, 0x418380, 0x00000016);
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nv_wr32(dev, 0x418400, 0x38004e00);
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nv_wr32(dev, 0x418404, 0x71e0ffff);
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@ -1728,7 +1728,7 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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// GPC_BROADCAST.TP_BROADCAST
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/* GPC_BROADCAST.TP_BROADCAST */
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nv_wr32(dev, 0x419848, 0x00000000);
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nv_wr32(dev, 0x419864, 0x0000012a);
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nv_wr32(dev, 0x419888, 0x00000000);
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@ -1741,7 +1741,7 @@ nvc0_grctx_generate_tp(struct drm_device *dev)
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nv_wr32(dev, 0x419a1c, 0x00000000);
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nv_wr32(dev, 0x419a20, 0x00000800);
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if (dev_priv->chipset != 0xc0)
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nv_wr32(dev, 0x00419ac4, 0x0007f440); // 0xc3
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nv_wr32(dev, 0x00419ac4, 0x0007f440); /* 0xc3 */
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nv_wr32(dev, 0x419b00, 0x0a418820);
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nv_wr32(dev, 0x419b04, 0x062080e6);
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nv_wr32(dev, 0x419b08, 0x020398a4);
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@ -1912,13 +1912,13 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
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for (i = 1; i < 7; i++)
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data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
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// GPC_BROADCAST
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/* GPC_BROADCAST */
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nv_wr32(dev, 0x418bb8, (priv->tp_total << 8) |
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priv->magic_not_rop_nr);
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for (i = 0; i < 6; i++)
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nv_wr32(dev, 0x418b08 + (i * 4), data[i]);
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// GPC_BROADCAST.TP_BROADCAST
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/* GPC_BROADCAST.TP_BROADCAST */
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nv_wr32(dev, 0x419bd0, (priv->tp_total << 8) |
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priv->magic_not_rop_nr |
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data2[0]);
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@ -1926,7 +1926,7 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
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for (i = 0; i < 6; i++)
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nv_wr32(dev, 0x419b00 + (i * 4), data[i]);
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// UNK78xx
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/* UNK78xx */
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nv_wr32(dev, 0x4078bc, (priv->tp_total << 8) |
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priv->magic_not_rop_nr);
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for (i = 0; i < 6; i++)
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@ -1944,7 +1944,7 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
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gpc = -1;
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for (i = 0, gpc = -1; i < 32; i++) {
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int ltp = i * (priv->tp_total - 1) / 32;
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do {
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gpc = (gpc + 1) % priv->gpc_nr;
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} while (!tpnr[gpc]);
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