mmc: sd: add support for signal voltage switch procedure
Host Controller v3.00 adds another Capabilities register. Apart from other things, this new register indicates whether the Host Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec doesn't mention about explicit support for SDR12 and SDR25 UHS-I modes, so the Host Controller v3.00 should support them by default. Also if the controller supports SDR104 mode, it will also support SDR50 mode as well. So depending on the host support, we set the corresponding MMC_CAP_* flags. One more new register. Host Control2 is added in v3.00, which is used during Signal Voltage Switch procedure described below. Since as per v3.00 spec, UHS-I supported hosts should set S18R to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also need to set XPC (bit 28) of OCR in case the host can supply >150mA. This support is indicated by the Maximum Current Capabilities register of the Host Controller. If the response of ACMD41 has both CCS and S18A set, we start the signal voltage switch procedure, which if successfull, will switch the card from 3.3V signalling to 1.8V signalling. Signal voltage switch procedure adds support for a new command CMD11 in the Physical Layer Spec v3.01. As part of this procedure, we need to set 1.8V Signalling Enable (bit 3) of Host Control2 register, which if remains set after 5ms, means the switch to 1.8V signalling is successfull. Otherwise, we clear bit 24 of OCR and retry the initialization sequence. When we remove the card, and insert the same or another card, we need to make sure that we start with 3.3V signalling voltage. So we call mmc_set_signal_voltage() with MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling voltage before we actually start initializing the card. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Arindam Nath
Chris Ball
parent
cb87ea28ed
commit
f2119df6b7
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@ -942,6 +942,38 @@ u32 mmc_select_voltage(struct mmc_host *host, u32 ocr)
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return ocr;
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}
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int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage)
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{
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struct mmc_command cmd = {0};
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int err = 0;
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BUG_ON(!host);
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/*
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* Send CMD11 only if the request is to switch the card to
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* 1.8V signalling.
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*/
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if (signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
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cmd.opcode = SD_SWITCH_VOLTAGE;
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cmd.arg = 0;
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cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
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err = mmc_wait_for_cmd(host, &cmd, 0);
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if (err)
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return err;
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if (!mmc_host_is_spi(host) && (cmd.resp[0] & R1_ERROR))
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return -EIO;
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}
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host->ios.signal_voltage = signal_voltage;
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if (host->ops->start_signal_voltage_switch)
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err = host->ops->start_signal_voltage_switch(host, &host->ios);
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return err;
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}
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/*
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* Select timing parameters for host.
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*/
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@ -41,6 +41,7 @@ void mmc_set_bus_width(struct mmc_host *host, unsigned int width);
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void mmc_set_bus_width_ddr(struct mmc_host *host, unsigned int width,
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unsigned int ddr);
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u32 mmc_select_voltage(struct mmc_host *host, u32 ocr);
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int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage);
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void mmc_set_timing(struct mmc_host *host, unsigned int timing);
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static inline void mmc_delay(unsigned int ms)
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@ -403,6 +403,7 @@ struct device_type sd_type = {
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int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid)
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{
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int err;
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u32 rocr;
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/*
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* Since we're changing the OCR value, we seem to
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@ -420,12 +421,38 @@ int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid)
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*/
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err = mmc_send_if_cond(host, ocr);
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if (!err)
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ocr |= 1 << 30;
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ocr |= SD_OCR_CCS;
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err = mmc_send_app_op_cond(host, ocr, NULL);
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/*
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* If the host supports one of UHS-I modes, request the card
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* to switch to 1.8V signaling level.
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*/
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if (host->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
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MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50))
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ocr |= SD_OCR_S18R;
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/* If the host can supply more than 150mA, XPC should be set to 1. */
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if (host->caps & (MMC_CAP_SET_XPC_330 | MMC_CAP_SET_XPC_300 |
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MMC_CAP_SET_XPC_180))
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ocr |= SD_OCR_XPC;
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try_again:
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err = mmc_send_app_op_cond(host, ocr, &rocr);
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if (err)
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return err;
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/*
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* In case CCS and S18A in the response is set, start Signal Voltage
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* Switch procedure. SPI mode doesn't support CMD11.
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*/
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if (!mmc_host_is_spi(host) && ((rocr & 0x41000000) == 0x41000000)) {
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err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180);
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if (err) {
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ocr &= ~SD_OCR_S18R;
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goto try_again;
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}
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}
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if (mmc_host_is_spi(host))
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err = mmc_send_cid(host, cid);
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else
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@ -773,6 +800,11 @@ int mmc_attach_sd(struct mmc_host *host)
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BUG_ON(!host);
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WARN_ON(!host->claimed);
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/* Make sure we are at 3.3V signalling voltage */
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err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330);
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if (err)
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return err;
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err = mmc_send_app_op_cond(host, 0, &ocr);
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if (err)
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return err;
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@ -83,6 +83,8 @@ static void sdhci_dumpregs(struct sdhci_host *host)
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printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
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sdhci_readw(host, SDHCI_COMMAND),
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sdhci_readl(host, SDHCI_MAX_CURRENT));
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printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
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sdhci_readw(host, SDHCI_HOST_CONTROL2));
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if (host->flags & SDHCI_USE_ADMA)
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printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
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@ -1323,11 +1325,114 @@ out:
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spin_unlock_irqrestore(&host->lock, flags);
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}
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static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
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struct mmc_ios *ios)
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{
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struct sdhci_host *host;
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u8 pwr;
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u16 clk, ctrl;
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u32 present_state;
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host = mmc_priv(mmc);
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/*
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* Signal Voltage Switching is only applicable for Host Controllers
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* v3.00 and above.
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*/
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if (host->version < SDHCI_SPEC_300)
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return 0;
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/*
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* We first check whether the request is to set signalling voltage
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* to 3.3V. If so, we change the voltage to 3.3V and return quickly.
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*/
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
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/* Set 1.8V Signal Enable in the Host Control2 register to 0 */
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ctrl &= ~SDHCI_CTRL_VDD_180;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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/* Wait for 5ms */
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usleep_range(5000, 5500);
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/* 3.3V regulator output should be stable within 5 ms */
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (!(ctrl & SDHCI_CTRL_VDD_180))
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return 0;
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else {
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printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
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"signalling voltage failed\n");
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return -EIO;
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}
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} else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
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(ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
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/* Stop SDCLK */
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk &= ~SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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/* Check whether DAT[3:0] is 0000 */
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present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
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if (!((present_state & SDHCI_DATA_LVL_MASK) >>
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SDHCI_DATA_LVL_SHIFT)) {
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/*
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* Enable 1.8V Signal Enable in the Host Control2
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* register
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*/
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ctrl |= SDHCI_CTRL_VDD_180;
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sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
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/* Wait for 5ms */
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usleep_range(5000, 5500);
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ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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if (ctrl & SDHCI_CTRL_VDD_180) {
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/* Provide SDCLK again and wait for 1ms*/
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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clk |= SDHCI_CLOCK_CARD_EN;
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sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
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usleep_range(1000, 1500);
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/*
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* If DAT[3:0] level is 1111b, then the card
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* was successfully switched to 1.8V signaling.
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*/
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present_state = sdhci_readl(host,
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SDHCI_PRESENT_STATE);
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if ((present_state & SDHCI_DATA_LVL_MASK) ==
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SDHCI_DATA_LVL_MASK)
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return 0;
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}
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}
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/*
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* If we are here, that means the switch to 1.8V signaling
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* failed. We power cycle the card, and retry initialization
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* sequence by setting S18R to 0.
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*/
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pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
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pwr &= ~SDHCI_POWER_ON;
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sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
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/* Wait for 1ms as per the spec */
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usleep_range(1000, 1500);
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pwr |= SDHCI_POWER_ON;
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sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
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printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
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"voltage failed, retrying with S18R set to 0\n");
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return -EAGAIN;
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} else
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/* No signal voltage switch required */
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return 0;
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}
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static const struct mmc_host_ops sdhci_ops = {
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.request = sdhci_request,
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.set_ios = sdhci_set_ios,
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.get_ro = sdhci_get_ro,
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.enable_sdio_irq = sdhci_enable_sdio_irq,
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.start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
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};
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/*****************************************************************************\
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@ -1808,7 +1913,9 @@ EXPORT_SYMBOL_GPL(sdhci_alloc_host);
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int sdhci_add_host(struct sdhci_host *host)
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{
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struct mmc_host *mmc;
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unsigned int caps, ocr_avail;
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u32 caps[2];
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u32 max_current_caps;
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unsigned int ocr_avail;
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int ret;
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WARN_ON(host == NULL);
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@ -1831,12 +1938,15 @@ int sdhci_add_host(struct sdhci_host *host)
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host->version);
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}
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caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
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caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
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sdhci_readl(host, SDHCI_CAPABILITIES);
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caps[1] = (host->version >= SDHCI_SPEC_300) ?
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sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
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if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
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host->flags |= SDHCI_USE_SDMA;
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else if (!(caps & SDHCI_CAN_DO_SDMA))
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else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
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DBG("Controller doesn't have SDMA capability\n");
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else
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host->flags |= SDHCI_USE_SDMA;
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@ -1847,7 +1957,8 @@ int sdhci_add_host(struct sdhci_host *host)
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host->flags &= ~SDHCI_USE_SDMA;
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}
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if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
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if ((host->version >= SDHCI_SPEC_200) &&
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(caps[0] & SDHCI_CAN_DO_ADMA2))
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host->flags |= SDHCI_USE_ADMA;
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if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
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@ -1897,10 +2008,10 @@ int sdhci_add_host(struct sdhci_host *host)
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}
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if (host->version >= SDHCI_SPEC_300)
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host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
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host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
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>> SDHCI_CLOCK_BASE_SHIFT;
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else
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host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
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host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
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>> SDHCI_CLOCK_BASE_SHIFT;
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host->max_clk *= 1000000;
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@ -1916,7 +2027,7 @@ int sdhci_add_host(struct sdhci_host *host)
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}
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host->timeout_clk =
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(caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
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(caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
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if (host->timeout_clk == 0) {
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if (host->ops->get_timeout_clock) {
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host->timeout_clk = host->ops->get_timeout_clock(host);
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@ -1928,7 +2039,7 @@ int sdhci_add_host(struct sdhci_host *host)
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return -ENODEV;
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}
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}
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if (caps & SDHCI_TIMEOUT_CLK_UNIT)
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if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
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host->timeout_clk *= 1000;
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/*
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@ -1955,21 +2066,76 @@ int sdhci_add_host(struct sdhci_host *host)
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if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
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mmc->caps |= MMC_CAP_4_BIT_DATA;
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if (caps & SDHCI_CAN_DO_HISPD)
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if (caps[0] & SDHCI_CAN_DO_HISPD)
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mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
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if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
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mmc_card_is_removable(mmc))
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mmc->caps |= MMC_CAP_NEEDS_POLL;
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/* UHS-I mode(s) supported by the host controller. */
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if (host->version >= SDHCI_SPEC_300)
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mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
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/* SDR104 supports also implies SDR50 support */
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if (caps[1] & SDHCI_SUPPORT_SDR104)
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mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
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else if (caps[1] & SDHCI_SUPPORT_SDR50)
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mmc->caps |= MMC_CAP_UHS_SDR50;
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if (caps[1] & SDHCI_SUPPORT_DDR50)
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mmc->caps |= MMC_CAP_UHS_DDR50;
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ocr_avail = 0;
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if (caps & SDHCI_CAN_VDD_330)
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/*
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* According to SD Host Controller spec v3.00, if the Host System
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* can afford more than 150mA, Host Driver should set XPC to 1. Also
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* the value is meaningful only if Voltage Support in the Capabilities
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* register is set. The actual current value is 4 times the register
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* value.
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*/
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max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
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if (caps[0] & SDHCI_CAN_VDD_330) {
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int max_current_330;
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ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
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if (caps & SDHCI_CAN_VDD_300)
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max_current_330 = ((max_current_caps &
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SDHCI_MAX_CURRENT_330_MASK) >>
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SDHCI_MAX_CURRENT_330_SHIFT) *
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SDHCI_MAX_CURRENT_MULTIPLIER;
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if (max_current_330 > 150)
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mmc->caps |= MMC_CAP_SET_XPC_330;
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}
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if (caps[0] & SDHCI_CAN_VDD_300) {
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int max_current_300;
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ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
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if (caps & SDHCI_CAN_VDD_180)
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max_current_300 = ((max_current_caps &
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SDHCI_MAX_CURRENT_300_MASK) >>
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SDHCI_MAX_CURRENT_300_SHIFT) *
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SDHCI_MAX_CURRENT_MULTIPLIER;
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if (max_current_300 > 150)
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mmc->caps |= MMC_CAP_SET_XPC_300;
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}
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if (caps[0] & SDHCI_CAN_VDD_180) {
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int max_current_180;
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ocr_avail |= MMC_VDD_165_195;
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max_current_180 = ((max_current_caps &
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SDHCI_MAX_CURRENT_180_MASK) >>
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SDHCI_MAX_CURRENT_180_SHIFT) *
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SDHCI_MAX_CURRENT_MULTIPLIER;
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if (max_current_180 > 150)
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mmc->caps |= MMC_CAP_SET_XPC_180;
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}
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mmc->ocr_avail = ocr_avail;
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mmc->ocr_avail_sdio = ocr_avail;
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if (host->ocr_avail_sdio)
|
||||
|
|
@ -2029,7 +2195,7 @@ int sdhci_add_host(struct sdhci_host *host)
|
|||
if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
|
||||
mmc->max_blk_size = 2;
|
||||
} else {
|
||||
mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
|
||||
mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
|
||||
SDHCI_MAX_BLOCK_SHIFT;
|
||||
if (mmc->max_blk_size >= 3) {
|
||||
printk(KERN_WARNING "%s: Invalid maximum block size, "
|
||||
|
|
|
|||
|
|
@ -68,6 +68,8 @@
|
|||
#define SDHCI_DATA_AVAILABLE 0x00000800
|
||||
#define SDHCI_CARD_PRESENT 0x00010000
|
||||
#define SDHCI_WRITE_PROTECT 0x00080000
|
||||
#define SDHCI_DATA_LVL_MASK 0x00F00000
|
||||
#define SDHCI_DATA_LVL_SHIFT 20
|
||||
|
||||
#define SDHCI_HOST_CONTROL 0x28
|
||||
#define SDHCI_CTRL_LED 0x01
|
||||
|
|
@ -146,7 +148,8 @@
|
|||
|
||||
#define SDHCI_ACMD12_ERR 0x3C
|
||||
|
||||
/* 3E-3F reserved */
|
||||
#define SDHCI_HOST_CONTROL2 0x3E
|
||||
#define SDHCI_CTRL_VDD_180 0x0008
|
||||
|
||||
#define SDHCI_CAPABILITIES 0x40
|
||||
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
|
||||
|
|
@ -167,9 +170,20 @@
|
|||
#define SDHCI_CAN_VDD_180 0x04000000
|
||||
#define SDHCI_CAN_64BIT 0x10000000
|
||||
|
||||
#define SDHCI_SUPPORT_SDR50 0x00000001
|
||||
#define SDHCI_SUPPORT_SDR104 0x00000002
|
||||
#define SDHCI_SUPPORT_DDR50 0x00000004
|
||||
|
||||
#define SDHCI_CAPABILITIES_1 0x44
|
||||
|
||||
#define SDHCI_MAX_CURRENT 0x48
|
||||
#define SDHCI_MAX_CURRENT 0x48
|
||||
#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
|
||||
#define SDHCI_MAX_CURRENT_330_SHIFT 0
|
||||
#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
|
||||
#define SDHCI_MAX_CURRENT_300_SHIFT 8
|
||||
#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
|
||||
#define SDHCI_MAX_CURRENT_180_SHIFT 16
|
||||
#define SDHCI_MAX_CURRENT_MULTIPLIER 4
|
||||
|
||||
/* 4C-4F reserved for more max current */
|
||||
|
||||
|
|
|
|||
|
|
@ -56,6 +56,11 @@ struct mmc_ios {
|
|||
#define MMC_SDR_MODE 0
|
||||
#define MMC_1_2V_DDR_MODE 1
|
||||
#define MMC_1_8V_DDR_MODE 2
|
||||
|
||||
unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */
|
||||
|
||||
#define MMC_SIGNAL_VOLTAGE_330 0
|
||||
#define MMC_SIGNAL_VOLTAGE_180 1
|
||||
};
|
||||
|
||||
struct mmc_host_ops {
|
||||
|
|
@ -117,6 +122,8 @@ struct mmc_host_ops {
|
|||
|
||||
/* optional callback for HC quirks */
|
||||
void (*init_card)(struct mmc_host *host, struct mmc_card *card);
|
||||
|
||||
int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios);
|
||||
};
|
||||
|
||||
struct mmc_card;
|
||||
|
|
@ -173,6 +180,14 @@ struct mmc_host {
|
|||
/* DDR mode at 1.2V */
|
||||
#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
|
||||
#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
|
||||
#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
|
||||
#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
|
||||
#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
|
||||
#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
|
||||
#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
|
||||
#define MMC_CAP_SET_XPC_330 (1 << 20) /* Host supports >150mA current at 3.3V */
|
||||
#define MMC_CAP_SET_XPC_300 (1 << 21) /* Host supports >150mA current at 3.0V */
|
||||
#define MMC_CAP_SET_XPC_180 (1 << 22) /* Host supports >150mA current at 1.8V */
|
||||
|
||||
mmc_pm_flag_t pm_caps; /* supported pm features */
|
||||
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
/* This is basically the same command as for MMC with some quirks. */
|
||||
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
|
||||
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
|
||||
#define SD_SWITCH_VOLTAGE 11 /* ac R1 */
|
||||
|
||||
/* class 10 */
|
||||
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
|
||||
|
|
@ -32,6 +33,12 @@
|
|||
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
|
||||
#define SD_APP_SEND_SCR 51 /* adtc R1 */
|
||||
|
||||
/* OCR bit definitions */
|
||||
#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */
|
||||
#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
|
||||
#define SD_OCR_XPC (1 << 28) /* SDXC power control */
|
||||
#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
|
||||
|
||||
/*
|
||||
* SD_SWITCH argument format:
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue