[SCSI] mvsas: add support for 94xx phy tuning and multiple revisions
Add 94xx phy tuning to aid manufacturing. Add support for 94xx multiple revisions: A0, B0, C0, C1, C2. Signed-off-by: Xiangliang Yu <yuxiangl@marvell.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Xiangliang Yu
James Bottomley
parent
534ff10104
commit
f1f82a919d
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@ -48,6 +48,216 @@ static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i)
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}
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}
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void set_phy_tuning(struct mvs_info *mvi, int phy_id,
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struct phy_tuning phy_tuning)
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{
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u32 tmp, setting_0 = 0, setting_1 = 0;
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u8 i;
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/* Remap information for B0 chip:
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*
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* R0Ch -> R118h[15:0] (Adapted DFE F3 - F5 coefficient)
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* R0Dh -> R118h[31:16] (Generation 1 Setting 0)
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* R0Eh -> R11Ch[15:0] (Generation 1 Setting 1)
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* R0Fh -> R11Ch[31:16] (Generation 2 Setting 0)
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* R10h -> R120h[15:0] (Generation 2 Setting 1)
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* R11h -> R120h[31:16] (Generation 3 Setting 0)
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* R12h -> R124h[15:0] (Generation 3 Setting 1)
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* R13h -> R124h[31:16] (Generation 4 Setting 0 (Reserved))
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*/
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/* A0 has a different set of registers */
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if (mvi->pdev->revision == VANIR_A0_REV)
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return;
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for (i = 0; i < 3; i++) {
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/* loop 3 times, set Gen 1, Gen 2, Gen 3 */
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switch (i) {
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case 0:
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setting_0 = GENERATION_1_SETTING;
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setting_1 = GENERATION_1_2_SETTING;
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break;
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case 1:
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setting_0 = GENERATION_1_2_SETTING;
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setting_1 = GENERATION_2_3_SETTING;
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break;
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case 2:
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setting_0 = GENERATION_2_3_SETTING;
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setting_1 = GENERATION_3_4_SETTING;
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break;
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}
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/* Set:
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*
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* Transmitter Emphasis Enable
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* Transmitter Emphasis Amplitude
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* Transmitter Amplitude
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*/
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mvs_write_port_vsr_addr(mvi, phy_id, setting_0);
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tmp = mvs_read_port_vsr_data(mvi, phy_id);
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tmp &= ~(0xFBE << 16);
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tmp |= (((phy_tuning.trans_emp_en << 11) |
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(phy_tuning.trans_emp_amp << 7) |
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(phy_tuning.trans_amp << 1)) << 16);
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mvs_write_port_vsr_data(mvi, phy_id, tmp);
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/* Set Transmitter Amplitude Adjust */
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mvs_write_port_vsr_addr(mvi, phy_id, setting_1);
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tmp = mvs_read_port_vsr_data(mvi, phy_id);
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tmp &= ~(0xC000);
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tmp |= (phy_tuning.trans_amp_adj << 14);
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mvs_write_port_vsr_data(mvi, phy_id, tmp);
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}
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}
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void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id,
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struct ffe_control ffe)
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{
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u32 tmp;
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/* Don't run this if A0/B0 */
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if ((mvi->pdev->revision == VANIR_A0_REV)
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|| (mvi->pdev->revision == VANIR_B0_REV))
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return;
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/* FFE Resistor and Capacitor */
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/* R10Ch DFE Resolution Control/Squelch and FFE Setting
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*
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* FFE_FORCE [7]
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* FFE_RES_SEL [6:4]
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* FFE_CAP_SEL [3:0]
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*/
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mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL);
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tmp = mvs_read_port_vsr_data(mvi, phy_id);
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tmp &= ~0xFF;
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/* Read from HBA_Info_Page */
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tmp |= ((0x1 << 7) |
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(ffe.ffe_rss_sel << 4) |
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(ffe.ffe_cap_sel << 0));
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mvs_write_port_vsr_data(mvi, phy_id, tmp);
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/* R064h PHY Mode Register 1
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*
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* DFE_DIS 18
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*/
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mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
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tmp = mvs_read_port_vsr_data(mvi, phy_id);
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tmp &= ~0x40001;
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/* Hard coding */
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/* No defines in HBA_Info_Page */
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tmp |= (0 << 18);
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mvs_write_port_vsr_data(mvi, phy_id, tmp);
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/* R110h DFE F0-F1 Coefficient Control/DFE Update Control
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*
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* DFE_UPDATE_EN [11:6]
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* DFE_FX_FORCE [5:0]
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*/
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mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL);
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tmp = mvs_read_port_vsr_data(mvi, phy_id);
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tmp &= ~0xFFF;
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/* Hard coding */
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/* No defines in HBA_Info_Page */
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tmp |= ((0x3F << 6) | (0x0 << 0));
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mvs_write_port_vsr_data(mvi, phy_id, tmp);
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/* R1A0h Interface and Digital Reference Clock Control/Reserved_50h
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*
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* FFE_TRAIN_EN 3
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*/
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mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);
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tmp = mvs_read_port_vsr_data(mvi, phy_id);
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tmp &= ~0x8;
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/* Hard coding */
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/* No defines in HBA_Info_Page */
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tmp |= (0 << 3);
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mvs_write_port_vsr_data(mvi, phy_id, tmp);
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}
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/*Notice: this function must be called when phy is disabled*/
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void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate)
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{
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union reg_phy_cfg phy_cfg, phy_cfg_tmp;
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mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
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phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id);
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phy_cfg.v = 0;
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phy_cfg.u.disable_phy = phy_cfg_tmp.u.disable_phy;
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phy_cfg.u.sas_support = 1;
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phy_cfg.u.sata_support = 1;
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phy_cfg.u.sata_host_mode = 1;
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switch (rate) {
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case 0x0:
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/* support 1.5 Gbps */
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phy_cfg.u.speed_support = 1;
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phy_cfg.u.snw_3_support = 0;
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phy_cfg.u.tx_lnk_parity = 1;
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phy_cfg.u.tx_spt_phs_lnk_rate = 0x30;
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break;
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case 0x1:
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/* support 1.5, 3.0 Gbps */
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phy_cfg.u.speed_support = 3;
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phy_cfg.u.tx_spt_phs_lnk_rate = 0x3c;
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phy_cfg.u.tx_lgcl_lnk_rate = 0x08;
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break;
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case 0x2:
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default:
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/* support 1.5, 3.0, 6.0 Gbps */
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phy_cfg.u.speed_support = 7;
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phy_cfg.u.snw_3_support = 1;
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phy_cfg.u.tx_lnk_parity = 1;
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phy_cfg.u.tx_spt_phs_lnk_rate = 0x3f;
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phy_cfg.u.tx_lgcl_lnk_rate = 0x09;
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break;
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}
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mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v);
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}
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static void __devinit
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mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id)
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{
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u32 temp;
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temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]);
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if (temp == 0xFFFFFFFFL) {
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mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6;
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mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A;
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mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3;
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}
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temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]);
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if (temp == 0xFFL) {
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switch (mvi->pdev->revision) {
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case VANIR_A0_REV:
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case VANIR_B0_REV:
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mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
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mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7;
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break;
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case VANIR_C0_REV:
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case VANIR_C1_REV:
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case VANIR_C2_REV:
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default:
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mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;
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mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC;
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break;
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}
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}
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temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]);
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if (temp == 0xFFL)
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/*set default phy_rate = 6Gbps*/
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mvi->hba_info_param.phy_rate[phy_id] = 0x2;
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set_phy_tuning(mvi, phy_id,
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mvi->hba_info_param.phy_tuning[phy_id]);
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set_phy_ffe_tuning(mvi, phy_id,
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mvi->hba_info_param.ffe_ctl[phy_id]);
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set_phy_rate(mvi, phy_id,
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mvi->hba_info_param.phy_rate[phy_id]);
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}
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static void __devinit mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)
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{
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void __iomem *regs = mvi->regs;
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@ -90,12 +300,25 @@ static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)
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static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
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{
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mvs_write_port_vsr_addr(mvi, phy_id, 0x1B4);
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mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
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mvs_write_port_vsr_addr(mvi, phy_id, 0x104);
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mvs_write_port_vsr_data(mvi, phy_id, 0x00018080);
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u32 tmp;
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u8 revision = 0;
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revision = mvi->pdev->revision;
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if (revision == VANIR_A0_REV) {
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mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
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mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);
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}
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if (revision == VANIR_B0_REV) {
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mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL);
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mvs_write_port_vsr_data(mvi, phy_id, 0x08001006);
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mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);
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mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f);
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}
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mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);
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mvs_write_port_vsr_data(mvi, phy_id, 0x00207fff);
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tmp = mvs_read_port_vsr_data(mvi, phy_id);
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tmp |= bit(0);
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mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff);
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}
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static int __devinit mvs_94xx_init(struct mvs_info *mvi)
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@ -103,7 +326,9 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi)
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void __iomem *regs = mvi->regs;
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int i;
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u32 tmp, cctl;
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u8 revision;
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revision = mvi->pdev->revision;
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mvs_show_pcie_usage(mvi);
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if (mvi->flags & MVF_FLAG_SOC) {
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tmp = mr32(MVS_PHY_CTL);
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@ -133,6 +358,28 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi)
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msleep(100);
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}
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/* disable Multiplexing, enable phy implemented */
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mw32(MVS_PORTS_IMP, 0xFF);
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if (revision == VANIR_A0_REV) {
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mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET);
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mw32(MVS_PA_VSR_PORT, 0x00018080);
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}
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mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2);
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if (revision == VANIR_A0_REV || revision == VANIR_B0_REV)
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/* set 6G/3G/1.5G, multiplexing, without SSC */
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mw32(MVS_PA_VSR_PORT, 0x0084d4fe);
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else
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/* set 6G/3G/1.5G, multiplexing, with and without SSC */
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mw32(MVS_PA_VSR_PORT, 0x0084fffe);
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if (revision == VANIR_B0_REV) {
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mw32(MVS_PA_VSR_ADDR, CMD_APP_MEM_CTL);
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mw32(MVS_PA_VSR_PORT, 0x08001006);
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mw32(MVS_PA_VSR_ADDR, CMD_HOST_RD_DATA);
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mw32(MVS_PA_VSR_PORT, 0x0000705f);
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}
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/* reset control */
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mw32(MVS_PCS, 0); /* MVS_PCS */
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mw32(MVS_STP_REG_SET_0, 0);
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@ -141,15 +388,6 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi)
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/* init phys */
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mvs_phy_hacks(mvi);
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/* disable Multiplexing, enable phy implemented */
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mw32(MVS_PORTS_IMP, 0xFF);
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mw32(MVS_PA_VSR_ADDR, 0x00000104);
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mw32(MVS_PA_VSR_PORT, 0x00018080);
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mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE8);
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mw32(MVS_PA_VSR_PORT, 0x0084ffff);
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/* set LED blink when IO*/
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mw32(MVS_PA_VSR_ADDR, 0x00000030);
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tmp = mr32(MVS_PA_VSR_PORT);
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@ -178,6 +416,7 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi)
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(mvi->phy[i].dev_sas_addr));
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mvs_94xx_enable_xmt(mvi, i);
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mvs_94xx_config_reg_from_hba(mvi, i);
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mvs_94xx_phy_enable(mvi, i);
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mvs_94xx_phy_reset(mvi, i, 1);
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@ -30,6 +30,14 @@
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#define MAX_LINK_RATE SAS_LINK_RATE_6_0_GBPS
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enum VANIR_REVISION_ID {
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VANIR_A0_REV = 0xA0,
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VANIR_B0_REV = 0x01,
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VANIR_C0_REV = 0x02,
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VANIR_C1_REV = 0x03,
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VANIR_C2_REV = 0xC2,
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};
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enum hw_registers {
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MVS_GBL_CTL = 0x04, /* global control */
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MVS_GBL_INT_STAT = 0x00, /* global irq status */
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@ -126,6 +134,10 @@ enum sas_sata_vsp_regs {
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VSR_PHY_MODE11 = 0x0B * 4, /* Phy Mode */
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VSR_PHY_VS0 = 0x0C * 4, /* Vednor Specific 0 */
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VSR_PHY_VS1 = 0x0D * 4, /* Vednor Specific 1 */
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VSR_PHY_FFE_CONTROL = 0x10C,
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VSR_PHY_DFE_UPDATE_CRTL = 0x110,
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VSR_REF_CLOCK_CRTL = 0x1A0,
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};
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enum chip_register_bits {
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@ -169,6 +181,41 @@ enum pci_interrupt_cause {
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IRQ_PCIE_ERR = (1 << 31),
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};
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union reg_phy_cfg {
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u32 v;
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struct {
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u32 phy_reset:1;
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u32 sas_support:1;
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u32 sata_support:1;
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u32 sata_host_mode:1;
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/*
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* bit 2: 6Gbps support
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* bit 1: 3Gbps support
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* bit 0: 1.5Gbps support
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*/
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u32 speed_support:3;
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u32 snw_3_support:1;
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u32 tx_lnk_parity:1;
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/*
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* bit 5: G1 (1.5Gbps) Without SSC
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* bit 4: G1 (1.5Gbps) with SSC
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* bit 3: G2 (3.0Gbps) Without SSC
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* bit 2: G2 (3.0Gbps) with SSC
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* bit 1: G3 (6.0Gbps) without SSC
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* bit 0: G3 (6.0Gbps) with SSC
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*/
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u32 tx_spt_phs_lnk_rate:6;
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/* 8h: 1.5Gbps 9h: 3Gbps Ah: 6Gbps */
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u32 tx_lgcl_lnk_rate:4;
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u32 tx_ssc_type:1;
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u32 sata_spin_up_spt:1;
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u32 sata_spin_up_en:1;
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u32 bypass_oob:1;
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u32 disable_phy:1;
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u32 rsvd:8;
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} u;
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};
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#define MAX_SG_ENTRY 255
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struct mvs_prd_imt {
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@ -185,6 +232,17 @@ struct mvs_prd {
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struct mvs_prd_imt im_len;
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} __attribute__ ((packed));
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/*
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* these registers are accessed through port vendor
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* specific address/data registers
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*/
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enum sas_sata_phy_regs {
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GENERATION_1_SETTING = 0x118,
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GENERATION_1_2_SETTING = 0x11C,
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GENERATION_2_3_SETTING = 0x120,
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GENERATION_3_4_SETTING = 0x124,
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};
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|
||||
#define SPI_CTRL_REG_94XX 0xc800
|
||||
#define SPI_ADDR_REG_94XX 0xc804
|
||||
#define SPI_WR_DATA_REG_94XX 0xc808
|
||||
|
|
|
|||
|
|
@ -569,6 +569,9 @@ static int __devinit mvs_pci_init(struct pci_dev *pdev,
|
|||
goto err_out_regions;
|
||||
}
|
||||
|
||||
memset(&mvi->hba_info_param, 0xFF,
|
||||
sizeof(struct hba_info_page));
|
||||
|
||||
mvs_init_sas_add(mvi);
|
||||
|
||||
mvi->instance = nhost;
|
||||
|
|
|
|||
|
|
@ -250,6 +250,73 @@ struct mvs_device {
|
|||
u16 reserved;
|
||||
};
|
||||
|
||||
/* Generate PHY tunning parameters */
|
||||
struct phy_tuning {
|
||||
/* 1 bit, transmitter emphasis enable */
|
||||
u8 trans_emp_en:1;
|
||||
/* 4 bits, transmitter emphasis amplitude */
|
||||
u8 trans_emp_amp:4;
|
||||
/* 3 bits, reserved space */
|
||||
u8 Reserved_2bit_1:3;
|
||||
/* 5 bits, transmitter amplitude */
|
||||
u8 trans_amp:5;
|
||||
/* 2 bits, transmitter amplitude adjust */
|
||||
u8 trans_amp_adj:2;
|
||||
/* 1 bit, reserved space */
|
||||
u8 resv_2bit_2:1;
|
||||
/* 2 bytes, reserved space */
|
||||
u8 reserved[2];
|
||||
};
|
||||
|
||||
struct ffe_control {
|
||||
/* 4 bits, FFE Capacitor Select (value range 0~F) */
|
||||
u8 ffe_cap_sel:4;
|
||||
/* 3 bits, FFE Resistor Select (value range 0~7) */
|
||||
u8 ffe_rss_sel:3;
|
||||
/* 1 bit reserve*/
|
||||
u8 reserved:1;
|
||||
};
|
||||
|
||||
/*
|
||||
* HBA_Info_Page is saved in Flash/NVRAM, total 256 bytes.
|
||||
* The data area is valid only Signature="MRVL".
|
||||
* If any member fills with 0xFF, the member is invalid.
|
||||
*/
|
||||
struct hba_info_page {
|
||||
/* Dword 0 */
|
||||
/* 4 bytes, structure signature,should be "MRVL" at first initial */
|
||||
u8 signature[4];
|
||||
|
||||
/* Dword 1-13 */
|
||||
u32 reserved1[13];
|
||||
|
||||
/* Dword 14-29 */
|
||||
/* 64 bytes, SAS address for each port */
|
||||
u64 sas_addr[8];
|
||||
|
||||
/* Dword 30-31 */
|
||||
/* 8 bytes for vanir 8 port PHY FFE seeting
|
||||
* BIT 0~3 : FFE Capacitor select(value range 0~F)
|
||||
* BIT 4~6 : FFE Resistor select(value range 0~7)
|
||||
* BIT 7: reserve.
|
||||
*/
|
||||
|
||||
struct ffe_control ffe_ctl[8];
|
||||
/* Dword 32 -43 */
|
||||
u32 reserved2[12];
|
||||
|
||||
/* Dword 44-45 */
|
||||
/* 8 bytes, 0: 1.5G, 1: 3.0G, should be 0x01 at first initial */
|
||||
u8 phy_rate[8];
|
||||
|
||||
/* Dword 46-53 */
|
||||
/* 32 bytes, PHY tuning parameters for each PHY*/
|
||||
struct phy_tuning phy_tuning[8];
|
||||
|
||||
/* Dword 54-63 */
|
||||
u32 reserved3[10];
|
||||
}; /* total 256 bytes */
|
||||
|
||||
struct mvs_slot_info {
|
||||
struct list_head entry;
|
||||
union {
|
||||
|
|
@ -338,6 +405,7 @@ struct mvs_info {
|
|||
u32 flashsectSize;
|
||||
|
||||
void *addon;
|
||||
struct hba_info_page hba_info_param;
|
||||
struct mvs_device devices[MVS_MAX_DEVICES];
|
||||
#ifndef DISABLE_HOTPLUG_DMA_FIX
|
||||
void *bulk_buffer;
|
||||
|
|
|
|||
Loading…
Reference in New Issue