drm/i915/vlv_dsi: conversion to drm_device based logging macros.
Converts the printk based logging macros to the struct drm_device based
logging macros in i915/display/vlv_dsi.c.
This was done using the following coccinelle script that transforms
based on the existence of a drm_i915_private device pointer.
@@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Checkpatch warnings were addressed manually.
Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200130083229.12889-3-wambui.karugax@gmail.com
This commit is contained in:
Wambui Karuga
Jani Nikula
parent
b2f7c0f1d8
commit
f1f76d7a3c
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@ -85,7 +85,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
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if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port),
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mask, 100))
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DRM_ERROR("DPI FIFOs are not empty\n");
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drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n");
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}
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static void write_data(struct drm_i915_private *dev_priv,
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@ -154,7 +154,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
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if (packet.payload_length) {
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if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
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data_mask, 50))
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DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
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drm_err(&dev_priv->drm,
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"Timeout waiting for HS/LP DATA FIFO !full\n");
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write_data(dev_priv, data_reg, packet.payload,
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packet.payload_length);
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@ -167,7 +168,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
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if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
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ctrl_mask, 50)) {
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DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
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drm_err(&dev_priv->drm,
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"Timeout waiting for HS/LP CTRL FIFO !full\n");
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}
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intel_de_write(dev_priv, ctrl_reg,
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@ -178,7 +180,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
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data_mask = GEN_READ_DATA_AVAIL;
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if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
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data_mask, 50))
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DRM_ERROR("Timeout waiting for read data.\n");
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drm_err(&dev_priv->drm,
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"Timeout waiting for read data.\n");
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read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
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}
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@ -229,13 +232,15 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
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/* XXX: old code skips write if control unchanged */
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if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)))
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DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
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drm_dbg_kms(&dev_priv->drm,
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"Same special packet %02x twice in a row.\n", cmd);
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intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd);
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mask = SPL_PKT_SENT_INTERRUPT;
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if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
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DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
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drm_err(&dev_priv->drm,
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"Video mode command 0x%08x send failed.\n", cmd);
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return 0;
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}
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@ -267,7 +272,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
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struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
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int ret;
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DRM_DEBUG_KMS("\n");
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drm_dbg_kms(&dev_priv->drm, "\n");
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pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
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if (fixed_mode) {
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@ -354,7 +359,7 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder)
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
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GLK_MIPIIO_PORT_POWERED, 20))
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DRM_ERROR("MIPIO port is powergated\n");
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drm_err(&dev_priv->drm, "MIPIO port is powergated\n");
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}
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/* Check for cold boot scenario */
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@ -377,7 +382,7 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
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GLK_PHY_STATUS_PORT_READY, 20))
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DRM_ERROR("PHY is not ON\n");
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drm_err(&dev_priv->drm, "PHY is not ON\n");
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}
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/* Get IO out of reset */
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@ -403,7 +408,7 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
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/* Wait for ULPS active */
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if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
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GLK_ULPS_NOT_ACTIVE, 20))
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DRM_ERROR("ULPS not active\n");
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drm_err(&dev_priv->drm, "ULPS not active\n");
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/* Exit ULPS */
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val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));
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@ -427,14 +432,16 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
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GLK_DATA_LANE_STOP_STATE, 20))
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DRM_ERROR("Date lane not in STOP state\n");
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drm_err(&dev_priv->drm,
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"Date lane not in STOP state\n");
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}
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/* Wait for AFE LATCH */
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
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AFE_LATCHOUT, 20))
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DRM_ERROR("D-PHY not entering LP-11 state\n");
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drm_err(&dev_priv->drm,
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"D-PHY not entering LP-11 state\n");
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}
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}
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@ -445,7 +452,7 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder)
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enum port port;
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u32 val;
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DRM_DEBUG_KMS("\n");
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drm_dbg_kms(&dev_priv->drm, "\n");
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/* Enable MIPI PHY transparent latch */
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for_each_dsi_port(port, intel_dsi->ports) {
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@ -473,7 +480,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
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enum port port;
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u32 val;
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DRM_DEBUG_KMS("\n");
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drm_dbg_kms(&dev_priv->drm, "\n");
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vlv_flisdsi_get(dev_priv);
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/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
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@ -540,14 +547,15 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
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GLK_PHY_STATUS_PORT_READY, 20))
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DRM_ERROR("PHY is not turning OFF\n");
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drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
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}
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/* Wait for Pwr ACK bit to unset */
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
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GLK_MIPIIO_PORT_POWERED, 20))
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DRM_ERROR("MIPI IO Port is not powergated\n");
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drm_err(&dev_priv->drm,
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"MIPI IO Port is not powergated\n");
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}
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}
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@ -567,7 +575,7 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
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for_each_dsi_port(port, intel_dsi->ports) {
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if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
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GLK_PHY_STATUS_PORT_READY, 20))
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DRM_ERROR("PHY is not turning OFF\n");
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drm_err(&dev_priv->drm, "PHY is not turning OFF\n");
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}
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/* Clear MIPI mode */
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@ -590,7 +598,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
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enum port port;
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DRM_DEBUG_KMS("\n");
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drm_dbg_kms(&dev_priv->drm, "\n");
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for_each_dsi_port(port, intel_dsi->ports) {
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/* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
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i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
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@ -616,7 +624,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
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if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
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intel_de_wait_for_clear(dev_priv, port_ctrl,
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AFE_LATCHOUT, 30))
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DRM_ERROR("DSI LP not going Low\n");
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drm_err(&dev_priv->drm, "DSI LP not going Low\n");
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/* Disable MIPI PHY transparent latch */
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val = intel_de_read(dev_priv, port_ctrl);
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@ -764,7 +772,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
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u32 val;
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bool glk_cold_boot = false;
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DRM_DEBUG_KMS("\n");
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drm_dbg_kms(&dev_priv->drm, "\n");
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intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
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@ -907,7 +915,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
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enum port port;
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u32 val;
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DRM_DEBUG_KMS("\n");
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drm_dbg_kms(&dev_priv->drm, "\n");
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if (IS_GEN9_LP(dev_priv)) {
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intel_crtc_vblank_off(old_crtc_state);
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@ -982,7 +990,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
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enum port port;
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bool active = false;
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DRM_DEBUG_KMS("\n");
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drm_dbg_kms(&dev_priv->drm, "\n");
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wakeref = intel_display_power_get_if_enabled(dev_priv,
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encoder->power_domain);
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@ -1217,7 +1225,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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u32 pclk;
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DRM_DEBUG_KMS("\n");
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drm_dbg_kms(&dev_priv->drm, "\n");
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pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
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@ -1351,7 +1359,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
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u32 val, tmp;
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u16 mode_hdisplay;
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DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
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drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe));
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mode_hdisplay = adjusted_mode->crtc_hdisplay;
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@ -1727,7 +1735,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
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prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul);
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if (prepare_cnt > PREPARE_CNT_MAX) {
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DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt);
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drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",
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prepare_cnt);
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prepare_cnt = PREPARE_CNT_MAX;
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}
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@ -1747,7 +1756,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
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exit_zero_cnt += 1;
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if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) {
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DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt);
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drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",
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exit_zero_cnt);
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exit_zero_cnt = EXIT_ZERO_CNT_MAX;
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}
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@ -1757,7 +1767,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
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* ui_den, ui_num * mul);
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if (clk_zero_cnt > CLK_ZERO_CNT_MAX) {
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DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt);
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drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",
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clk_zero_cnt);
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clk_zero_cnt = CLK_ZERO_CNT_MAX;
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}
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@ -1766,7 +1777,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
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trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul);
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if (trail_cnt > TRAIL_CNT_MAX) {
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DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt);
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drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",
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trail_cnt);
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trail_cnt = TRAIL_CNT_MAX;
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}
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@ -1841,7 +1853,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
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enum port port;
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enum pipe pipe;
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DRM_DEBUG_KMS("\n");
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drm_dbg_kms(&dev_priv->drm, "\n");
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/* There is no detection method for MIPI so rely on VBT */
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if (!intel_bios_is_dsi_present(dev_priv, &port))
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@ -1920,18 +1932,18 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
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}
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if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
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DRM_DEBUG_KMS("no device found\n");
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drm_dbg_kms(&dev_priv->drm, "no device found\n");
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goto err;
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}
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/* Use clock read-back from current hw-state for fastboot */
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current_mode = intel_encoder_current_mode(intel_encoder);
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if (current_mode) {
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DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n",
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intel_dsi->pclk, current_mode->clock);
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drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",
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intel_dsi->pclk, current_mode->clock);
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if (intel_fuzzy_clock_check(intel_dsi->pclk,
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current_mode->clock)) {
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DRM_DEBUG_KMS("Using GOP pclk\n");
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drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n");
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intel_dsi->pclk = current_mode->clock;
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}
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@ -1959,7 +1971,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
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mutex_unlock(&dev->mode_config.mutex);
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if (!fixed_mode) {
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DRM_DEBUG_KMS("no fixed mode\n");
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drm_dbg_kms(&dev_priv->drm, "no fixed mode\n");
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goto err_cleanup_connector;
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}
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