drm/amd/display: After program backend, also program front end regs.
Issue: In case of two 4K@60 + one non-4k monitor, when unplug non-4k monitor, the remain two 4k monitor don't work properly. Reason: In that case, two 4k use two pipes and no split, when unplug happens, those two monitor will use 4 pipes and split, but on that time, frontend is not programed properly. Solution: After programed backend, front end should be programmed as per new pipe setting. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -806,7 +806,7 @@ bool dc_commit_streams(
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enum dc_status result = DC_ERROR_UNEXPECTED;
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struct validate_context *context;
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struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
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int i, j, k;
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int i, j;
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if (false == streams_changed(core_dc, streams, stream_count))
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return DC_OK;
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@ -862,18 +862,10 @@ bool dc_commit_streams(
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const struct core_sink *sink = context->streams[i]->sink;
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for (j = 0; j < context->stream_status[i].surface_count; j++) {
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const struct dc_surface *dc_surface =
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context->stream_status[i].surfaces[j];
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struct core_surface *surface =
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DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
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for (k = 0; k < context->res_ctx.pool->pipe_count; k++) {
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struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[k];
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if (dc_surface != &pipe->surface->public
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|| !dc_surface->visible)
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continue;
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pipe->tg->funcs->set_blank(pipe->tg, false);
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}
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core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
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}
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CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
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