From f196f0805b5b75f024481ab4dc65f60d86fe6441 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 3 Mar 2017 09:37:11 -0500 Subject: [PATCH] drm/amd/display: After program backend, also program front end regs. Issue: In case of two 4K@60 + one non-4k monitor, when unplug non-4k monitor, the remain two 4k monitor don't work properly. Reason: In that case, two 4k use two pipes and no split, when unplug happens, those two monitor will use 4 pipes and split, but on that time, frontend is not programed properly. Solution: After programed backend, front end should be programmed as per new pipe setting. Signed-off-by: Yongqiang Sun Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f1ec27365f56..a39b9987b9d6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -806,7 +806,7 @@ bool dc_commit_streams( enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; - int i, j, k; + int i, j; if (false == streams_changed(core_dc, streams, stream_count)) return DC_OK; @@ -862,18 +862,10 @@ bool dc_commit_streams( const struct core_sink *sink = context->streams[i]->sink; for (j = 0; j < context->stream_status[i].surface_count; j++) { - const struct dc_surface *dc_surface = - context->stream_status[i].surfaces[j]; + struct core_surface *surface = + DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]); - for (k = 0; k < context->res_ctx.pool->pipe_count; k++) { - struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[k]; - - if (dc_surface != &pipe->surface->public - || !dc_surface->visible) - continue; - - pipe->tg->funcs->set_blank(pipe->tg, false); - } + core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); } CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",