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ath9k_hw: avoid possible infinite loop in ar9003_get_pll_sqsum_dvc 

"ath9k: Fix softlockup in AR9485" with commit id
64bc1239c7 fixed the reported
issue, yet its better to avoid the possible infinite loop
in ar9003_get_pll_sqsum_dvc by having a timeout as suggested
by ath9k maintainers.
http://www.spinics.net/lists/linux-wireless/msg92126.html.
Based on my testing PLL's locking measurement is done in
~200us (2 iterations).

Cc: stable@vger.kernel.org
Cc: Rolf Offermanns <rolf.offermanns@gmx.net>
Cc: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Mohammed Shafi Shajakhan 2012-06-18 13:13:30 +05:30 committed by John W. Linville
parent a859e4d659
commit f18e3c6b67
1 changed files with 13 additions and 1 deletions
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14
drivers/net/wireless/ath/ath9k/hw.c
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@ -784,13 +784,25 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
{ {
struct ath_common *common = ath9k_hw_common(ah);
int i = 0;
REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
udelay(100); udelay(100);
REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
udelay(100); udelay(100);
if (WARN_ON_ONCE(i >= 100)) {
ath_err(common, "PLL4 meaurement not done\n");
break;
}
i++;
}
return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
} }
EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);