drm/amdgpu: get VCN harvest information from IP discovery table
Use the table rather than asic specific harvest registers. v2: remove harvesting register checking Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -470,6 +470,10 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
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switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
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case VCN_HWID:
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vcn_harvest_count++;
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if (harvest_info->list[i].number_instance == 0)
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adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
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else
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adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
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break;
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case DMU_HWID:
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adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
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@ -87,7 +87,6 @@ static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
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static int vcn_v3_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int i;
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if (amdgpu_sriov_vf(adev)) {
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adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
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@ -95,20 +94,10 @@ static int vcn_v3_0_early_init(void *handle)
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adev->vcn.num_enc_rings = 1;
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} else {
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if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 0)) {
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u32 harvest;
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for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
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harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
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if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
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adev->vcn.harvest_config |= 1 << i;
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}
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if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
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AMDGPU_VCN_HARVEST_VCN1))
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/* both instances are harvested, disable the block */
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return -ENOENT;
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}
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if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
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AMDGPU_VCN_HARVEST_VCN1))
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/* both instances are harvested, disable the block */
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return -ENOENT;
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if (adev->ip_versions[UVD_HWIP] == IP_VERSION(3, 0, 33))
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adev->vcn.num_enc_rings = 0;
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