xHCI-Add-XHCI_SLOWDOWN_QUIRK-quirk-for-phytium-xHCI

Since current Phytium Px210 xHCI host controller does not support
    USB Gen2(10Gbps) well, add the XHCI_SLOWDOWN_QUIRK quirk and
    modify the limited speed to 5Gbps.

    Signed-off-by: Feng Jun <fengjun@phytium.com.cn>
    Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>

(cherry picked from commit 50f3eecbba)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
This commit is contained in:
Mao Hongbo 2023-06-01 17:46:46 +08:00 committed by Jianping Liu
parent cb18a9e935
commit f13d8f3dcf
3 changed files with 11 additions and 0 deletions

View File

@ -2157,6 +2157,10 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
if (rhub->min_rev < minor_revision)
rhub->min_rev = minor_revision;
if (xhci->quirks & XHCI_SLOWDOWN_QUIRK)
if (major_revision == 0x03)
rhub->min_rev = 0;
/* Port offset and count in the third dword, see section 7.2 */
temp = readl(addr + 2);
port_offset = XHCI_EXT_PORT_OFF(temp);

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@ -43,6 +43,7 @@
#define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
#define PCI_DEVICE_ID_PHYTIUM_XHCI 0xdc27
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
@ -250,6 +251,11 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
if (pdev->vendor == PCI_VENDOR_ID_VIA)
xhci->quirks |= XHCI_RESET_ON_RESUME;
if (pdev->vendor == PCI_VENDOR_ID_PHYTIUM ||
pdev->device == PCI_DEVICE_ID_PHYTIUM_XHCI) {
xhci->quirks |= XHCI_SLOWDOWN_QUIRK;
}
/* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
if (pdev->vendor == PCI_VENDOR_ID_VIA &&
pdev->device == 0x3432)

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@ -1876,6 +1876,7 @@ struct xhci_hcd {
#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
#define XHCI_DISABLE_SPARSE BIT_ULL(38)
#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
#define XHCI_SLOWDOWN_QUIRK BIT_ULL(41)
unsigned int num_active_eps;
unsigned int limit_active_eps;