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clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL 

Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate
computed in sam9x60_frac_pll_recalc_rate() and the one computed in
sam9x60_frac_pll_compute_mul_frac().

Fixes: 43b1bb4a9b ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-8-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Claudiu Beznea 2021-10-11 14:27:11 +03:00 committed by Stephen Boyd
parent 5df4cd9099
commit f12d028b74
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/at91/clk-sam9x60-pll.c
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@ -73,8 +73,8 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
struct sam9x60_frac *frac = to_sam9x60_frac(core); struct sam9x60_frac *frac = to_sam9x60_frac(core);
return (parent_rate * (frac->mul + 1) + return parent_rate * (frac->mul + 1) +
((u64)parent_rate * frac->frac >> 22)); DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
} }
static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)