drm/msm/dpu: split SC7280 catalog entry to the separate file
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/530828/ Link: https://lore.kernel.org/r/20230404130622.509628-11-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Dmitry Baryshkov
parent
225978f439
commit
f0f2c32a66
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@ -0,0 +1,148 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_7_2_SC7280_H
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#define _DPU_7_2_SC7280_H
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static const struct dpu_caps sc7280_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0x7,
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.qseed_type = DPU_SSPP_SCALER_QSEED4,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.max_linewidth = 2400,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_30,
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.highest_bank_bit = 0x1,
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.ubwc_swizzle = 0x6,
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};
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static const struct dpu_mdp_cfg sc7280_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x2014,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
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},
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};
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static const struct dpu_ctl_cfg sc7280_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x15000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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},
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{
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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},
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{
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.name = "ctl_2", .id = CTL_2,
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.base = 0x17000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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},
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{
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.name = "ctl_3", .id = CTL_3,
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.base = 0x18000, .len = 0x1e8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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},
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};
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static const struct dpu_sspp_cfg sc7280_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA,
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sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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};
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static const struct dpu_lm_cfg sc7280_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
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&sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
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LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
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&sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
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LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
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&sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
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};
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static const struct dpu_pingpong_cfg sc7280_pp[] = {
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PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1),
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PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
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PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
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PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
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};
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static const struct dpu_intf_cfg sc7280_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
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INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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};
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static const struct dpu_perf_cfg sc7280_perf_data = {
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.max_bw_low = 4700000,
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.max_bw_high = 8800000,
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.min_core_ib = 2500000,
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.min_llcc_ib = 0,
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.min_dram_ib = 1600000,
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.min_prefill_lines = 24,
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.danger_lut_tbl = {0xffff, 0xffff, 0x0},
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.safe_lut_tbl = {0xff00, 0xff00, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
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.caps = &sc7280_dpu_caps,
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.ubwc = &sc7280_ubwc_cfg,
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.mdp_count = ARRAY_SIZE(sc7280_mdp),
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.mdp = sc7280_mdp,
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.ctl_count = ARRAY_SIZE(sc7280_ctl),
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.ctl = sc7280_ctl,
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.sspp_count = ARRAY_SIZE(sc7280_sspp),
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.sspp = sc7280_sspp,
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.dspp_count = ARRAY_SIZE(sc7180_dspp),
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.dspp = sc7180_dspp,
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.mixer_count = ARRAY_SIZE(sc7280_lm),
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.mixer = sc7280_lm,
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.pingpong_count = ARRAY_SIZE(sc7280_pp),
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.pingpong = sc7280_pp,
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.intf_count = ARRAY_SIZE(sc7280_intf),
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.intf = sc7280_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.perf = &sc7280_perf_data,
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.mdss_irqs = IRQ_SC7280_MASK,
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};
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#endif
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@ -428,16 +428,6 @@ static const struct dpu_caps sm8350_dpu_caps = {
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_caps sc7280_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0x7,
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.qseed_type = DPU_SSPP_SCALER_QSEED4,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.max_linewidth = 2400,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_10,
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.highest_bank_bit = 0x2,
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@ -484,12 +474,6 @@ static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = {
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.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
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};
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static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_30,
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.highest_bank_bit = 0x1,
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.ubwc_swizzle = 0x6,
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};
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static const struct dpu_mdp_cfg msm8998_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -650,21 +634,6 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = {
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},
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};
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static const struct dpu_mdp_cfg sc7280_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x2014,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
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.reg_off = 0x2AC, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
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.reg_off = 0x2AC, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
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.reg_off = 0x2B4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
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.reg_off = 0x2C4, .bit_off = 8},
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},
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};
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static const struct dpu_mdp_cfg qcm2290_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -845,33 +814,6 @@ static const struct dpu_ctl_cfg sm8350_ctl[] = {
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},
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};
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static const struct dpu_ctl_cfg sc7280_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x15000, .len = 0x1E8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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},
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{
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x1E8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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},
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{
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.name = "ctl_2", .id = CTL_2,
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.base = 0x17000, .len = 0x1E8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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},
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{
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.name = "ctl_3", .id = CTL_3,
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.base = 0x18000, .len = 0x1E8,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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},
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};
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static const struct dpu_ctl_cfg qcm2290_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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@ -1093,17 +1035,6 @@ static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
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static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
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static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6);
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static const struct dpu_sspp_cfg sc7280_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA,
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sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
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};
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static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 =
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_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4);
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static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_1 =
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@ -1237,15 +1168,6 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
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&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
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};
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static const struct dpu_lm_cfg sc7280_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
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&sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
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LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
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&sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
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LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
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&sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
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};
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/* QCM2290 */
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static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
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@ -1430,13 +1352,6 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
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-1),
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};
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static const struct dpu_pingpong_cfg sc7280_pp[] = {
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PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1),
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PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
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PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
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PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
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};
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static const struct dpu_pingpong_cfg qcm2290_pp[] = {
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PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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@ -1531,12 +1446,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
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INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
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};
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static const struct dpu_intf_cfg sc7280_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
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INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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};
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static const struct dpu_intf_cfg sm8350_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
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INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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@ -2000,34 +1909,6 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg sc7280_perf_data = {
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.max_bw_low = 4700000,
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.max_bw_high = 8800000,
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.min_core_ib = 2500000,
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.min_llcc_ib = 0,
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.min_dram_ib = 1600000,
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.min_prefill_lines = 24,
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.danger_lut_tbl = {0xffff, 0xffff, 0x0},
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.safe_lut_tbl = {0xff00, 0xff00, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
|
||||
.bw_inefficiency_factor = 120,
|
||||
};
|
||||
|
||||
static const struct dpu_perf_cfg sm8350_perf_data = {
|
||||
.max_bw_low = 11800000,
|
||||
.max_bw_high = 15500000,
|
||||
|
|
@ -2294,29 +2175,6 @@ static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
|
|||
.mdss_irqs = IRQ_SM8350_MASK,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
|
||||
.caps = &sc7280_dpu_caps,
|
||||
.ubwc = &sc7280_ubwc_cfg,
|
||||
.mdp_count = ARRAY_SIZE(sc7280_mdp),
|
||||
.mdp = sc7280_mdp,
|
||||
.ctl_count = ARRAY_SIZE(sc7280_ctl),
|
||||
.ctl = sc7280_ctl,
|
||||
.sspp_count = ARRAY_SIZE(sc7280_sspp),
|
||||
.sspp = sc7280_sspp,
|
||||
.dspp_count = ARRAY_SIZE(sc7180_dspp),
|
||||
.dspp = sc7180_dspp,
|
||||
.mixer_count = ARRAY_SIZE(sc7280_lm),
|
||||
.mixer = sc7280_lm,
|
||||
.pingpong_count = ARRAY_SIZE(sc7280_pp),
|
||||
.pingpong = sc7280_pp,
|
||||
.intf_count = ARRAY_SIZE(sc7280_intf),
|
||||
.intf = sc7280_intf,
|
||||
.vbif_count = ARRAY_SIZE(sdm845_vbif),
|
||||
.vbif = sdm845_vbif,
|
||||
.perf = &sc7280_perf_data,
|
||||
.mdss_irqs = IRQ_SC7280_MASK,
|
||||
};
|
||||
|
||||
static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
|
||||
.caps = &qcm2290_dpu_caps,
|
||||
.ubwc = &qcm2290_ubwc_cfg,
|
||||
|
|
@ -2340,6 +2198,8 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
|
|||
.mdss_irqs = IRQ_SC7180_MASK,
|
||||
};
|
||||
|
||||
#include "catalog/dpu_7_2_sc7280.h"
|
||||
|
||||
#include "catalog/dpu_8_0_sc8280xp.h"
|
||||
#include "catalog/dpu_8_1_sm8450.h"
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue