drm/amd/display: DCN1 link encoder
Create DCN1 link encoder files and update AUX and HPD register access. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Bernstein
Alex Deucher
parent
a944744ba5
commit
f0cd0a346d
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@ -11,8 +11,6 @@
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#include "dc_link_dp.h"
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#include "dc_link_ddc.h"
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#include "dm_helpers.h"
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#include "dce/dce_link_encoder.h"
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#include "dce/dce_stream_encoder.h"
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#include "dpcd_defs.h"
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enum dc_status core_link_read_dpcd(
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@ -26,7 +26,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \
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dcn10_dpp.o dcn10_opp.o dcn10_optc.o \
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dcn10_hubp.o dcn10_mpc.o \
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dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \
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dcn10_hubbub.o dcn10_stream_encoder.o
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dcn10_hubbub.o dcn10_stream_encoder.o dcn10_link_encoder.o
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AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,330 @@
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/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_LINK_ENCODER__DCN10_H__
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#define __DC_LINK_ENCODER__DCN10_H__
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#include "link_encoder.h"
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#define TO_DCN10_LINK_ENC(link_encoder)\
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container_of(link_encoder, struct dcn10_link_encoder, base)
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#define AUX_REG_LIST(id)\
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SRI(AUX_CONTROL, DP_AUX, id), \
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SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
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#define HPD_REG_LIST(id)\
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SRI(DC_HPD_CONTROL, HPD, id)
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#define LE_DCN_COMMON_REG_LIST(id) \
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SRI(DIG_BE_CNTL, DIG, id), \
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SRI(DIG_BE_EN_CNTL, DIG, id), \
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SRI(DP_CONFIG, DP, id), \
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SRI(DP_DPHY_CNTL, DP, id), \
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SRI(DP_DPHY_PRBS_CNTL, DP, id), \
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SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
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SRI(DP_DPHY_SYM0, DP, id), \
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SRI(DP_DPHY_SYM1, DP, id), \
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SRI(DP_DPHY_SYM2, DP, id), \
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SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
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SRI(DP_LINK_CNTL, DP, id), \
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SRI(DP_LINK_FRAMING_CNTL, DP, id), \
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SRI(DP_MSE_SAT0, DP, id), \
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SRI(DP_MSE_SAT1, DP, id), \
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SRI(DP_MSE_SAT2, DP, id), \
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SRI(DP_MSE_SAT_UPDATE, DP, id), \
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SRI(DP_SEC_CNTL, DP, id), \
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SRI(DP_VID_STREAM_CNTL, DP, id), \
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SRI(DP_DPHY_FAST_TRAINING, DP, id), \
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SRI(DP_SEC_CNTL1, DP, id), \
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SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
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SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
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SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
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#define LE_DCN10_REG_LIST(id)\
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LE_DCN_COMMON_REG_LIST(id)
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struct dcn10_link_enc_aux_registers {
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uint32_t AUX_CONTROL;
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uint32_t AUX_DPHY_RX_CONTROL0;
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};
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struct dcn10_link_enc_hpd_registers {
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uint32_t DC_HPD_CONTROL;
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};
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struct dcn10_link_enc_registers {
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uint32_t DIG_BE_CNTL;
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uint32_t DIG_BE_EN_CNTL;
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uint32_t DP_CONFIG;
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uint32_t DP_DPHY_CNTL;
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uint32_t DP_DPHY_INTERNAL_CTRL;
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uint32_t DP_DPHY_PRBS_CNTL;
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uint32_t DP_DPHY_SCRAM_CNTL;
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uint32_t DP_DPHY_SYM0;
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uint32_t DP_DPHY_SYM1;
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uint32_t DP_DPHY_SYM2;
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uint32_t DP_DPHY_TRAINING_PATTERN_SEL;
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uint32_t DP_LINK_CNTL;
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uint32_t DP_LINK_FRAMING_CNTL;
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uint32_t DP_MSE_SAT0;
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uint32_t DP_MSE_SAT1;
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uint32_t DP_MSE_SAT2;
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uint32_t DP_MSE_SAT_UPDATE;
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uint32_t DP_SEC_CNTL;
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uint32_t DP_VID_STREAM_CNTL;
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uint32_t DP_DPHY_FAST_TRAINING;
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uint32_t DP_DPHY_BS_SR_SWAP_CNTL;
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uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
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uint32_t DP_SEC_CNTL1;
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};
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#define LE_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\
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LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\
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LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\
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LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\
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LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\
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LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\
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LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\
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LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\
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LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\
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LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\
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LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\
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LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\
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LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\
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LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\
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LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\
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LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\
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LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\
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LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\
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LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\
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LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\
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LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\
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LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\
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LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\
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LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\
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LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\
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LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\
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LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\
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LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\
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LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\
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LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\
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LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
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LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\
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LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\
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LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\
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LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\
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LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\
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LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\
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LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\
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LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh)
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#define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \
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type DIG_ENABLE;\
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type DIG_HPD_SELECT;\
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type DIG_MODE;\
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type DIG_FE_SOURCE_SELECT;\
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type DPHY_BYPASS;\
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type DPHY_ATEST_SEL_LANE0;\
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type DPHY_ATEST_SEL_LANE1;\
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type DPHY_ATEST_SEL_LANE2;\
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type DPHY_ATEST_SEL_LANE3;\
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type DPHY_PRBS_EN;\
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type DPHY_PRBS_SEL;\
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type DPHY_SYM1;\
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type DPHY_SYM2;\
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type DPHY_SYM3;\
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type DPHY_SYM4;\
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type DPHY_SYM5;\
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type DPHY_SYM6;\
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type DPHY_SYM7;\
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type DPHY_SYM8;\
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type DPHY_SCRAMBLER_BS_COUNT;\
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type DPHY_SCRAMBLER_ADVANCE;\
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type DPHY_RX_FAST_TRAINING_CAPABLE;\
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type DPHY_LOAD_BS_COUNT;\
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type DPHY_TRAINING_PATTERN_SEL;\
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type DP_DPHY_HBR2_PATTERN_CONTROL;\
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type DP_LINK_TRAINING_COMPLETE;\
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type DP_IDLE_BS_INTERVAL;\
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type DP_VBID_DISABLE;\
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type DP_VID_ENHANCED_FRAME_MODE;\
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type DP_VID_STREAM_ENABLE;\
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type DP_UDI_LANES;\
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type DP_SEC_GSP0_LINE_NUM;\
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type DP_SEC_GSP0_PRIORITY;\
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type DP_MSE_SAT_SRC0;\
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type DP_MSE_SAT_SRC1;\
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type DP_MSE_SAT_SRC2;\
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type DP_MSE_SAT_SRC3;\
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type DP_MSE_SAT_SLOT_COUNT0;\
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type DP_MSE_SAT_SLOT_COUNT1;\
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type DP_MSE_SAT_SLOT_COUNT2;\
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type DP_MSE_SAT_SLOT_COUNT3;\
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type DP_MSE_SAT_UPDATE;\
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type DP_MSE_16_MTP_KEEPOUT;\
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type AUX_HPD_SEL;\
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type AUX_LS_READ_EN;\
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type AUX_RX_RECEIVE_WINDOW;\
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type DC_HPD_EN
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struct dcn10_link_enc_shift {
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DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
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};
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struct dcn10_link_enc_mask {
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DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
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};
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struct dcn10_link_encoder {
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struct link_encoder base;
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const struct dcn10_link_enc_registers *link_regs;
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const struct dcn10_link_enc_aux_registers *aux_regs;
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const struct dcn10_link_enc_hpd_registers *hpd_regs;
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const struct dcn10_link_enc_shift *link_shift;
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const struct dcn10_link_enc_mask *link_mask;
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};
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void dcn10_link_encoder_construct(
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struct dcn10_link_encoder *enc10,
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const struct encoder_init_data *init_data,
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const struct encoder_feature_support *enc_features,
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const struct dcn10_link_enc_registers *link_regs,
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const struct dcn10_link_enc_aux_registers *aux_regs,
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const struct dcn10_link_enc_hpd_registers *hpd_regs,
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const struct dcn10_link_enc_shift *link_shift,
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const struct dcn10_link_enc_mask *link_mask);
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bool dcn10_link_encoder_validate_dvi_output(
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const struct dcn10_link_encoder *enc10,
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enum signal_type connector_signal,
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enum signal_type signal,
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const struct dc_crtc_timing *crtc_timing);
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bool dcn10_link_encoder_validate_rgb_output(
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const struct dcn10_link_encoder *enc10,
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const struct dc_crtc_timing *crtc_timing);
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bool dcn10_link_encoder_validate_dp_output(
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const struct dcn10_link_encoder *enc10,
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const struct dc_crtc_timing *crtc_timing);
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bool dcn10_link_encoder_validate_wireless_output(
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const struct dcn10_link_encoder *enc10,
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const struct dc_crtc_timing *crtc_timing);
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bool dcn10_link_encoder_validate_output_with_stream(
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struct link_encoder *enc,
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const struct dc_stream_state *stream);
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/****************** HW programming ************************/
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/* initialize HW */ /* why do we initialze aux in here? */
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void dcn10_link_encoder_hw_init(struct link_encoder *enc);
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void dcn10_link_encoder_destroy(struct link_encoder **enc);
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/* program DIG_MODE in DIG_BE */
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/* TODO can this be combined with enable_output? */
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void dcn10_link_encoder_setup(
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struct link_encoder *enc,
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enum signal_type signal);
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/* enables TMDS PHY output */
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/* TODO: still need depth or just pass in adjusted pixel clock? */
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void dcn10_link_encoder_enable_tmds_output(
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struct link_encoder *enc,
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enum clock_source_id clock_source,
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enum dc_color_depth color_depth,
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enum signal_type signal,
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uint32_t pixel_clock);
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/* enables DP PHY output */
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void dcn10_link_encoder_enable_dp_output(
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struct link_encoder *enc,
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const struct dc_link_settings *link_settings,
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enum clock_source_id clock_source);
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/* enables DP PHY output in MST mode */
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void dcn10_link_encoder_enable_dp_mst_output(
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struct link_encoder *enc,
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const struct dc_link_settings *link_settings,
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enum clock_source_id clock_source);
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/* disable PHY output */
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void dcn10_link_encoder_disable_output(
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struct link_encoder *enc,
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enum signal_type signal);
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/* set DP lane settings */
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void dcn10_link_encoder_dp_set_lane_settings(
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struct link_encoder *enc,
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const struct link_training_settings *link_settings);
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void dcn10_link_encoder_dp_set_phy_pattern(
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struct link_encoder *enc,
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const struct encoder_set_dp_phy_pattern_param *param);
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/* programs DP MST VC payload allocation */
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void dcn10_link_encoder_update_mst_stream_allocation_table(
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struct link_encoder *enc,
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const struct link_mst_stream_allocation_table *table);
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void dcn10_link_encoder_connect_dig_be_to_fe(
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struct link_encoder *enc,
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enum engine_id engine,
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bool connect);
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void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
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struct link_encoder *enc,
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uint32_t index);
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void dcn10_link_encoder_enable_hpd(struct link_encoder *enc);
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void dcn10_link_encoder_disable_hpd(struct link_encoder *enc);
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void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
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bool exit_link_training_required);
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void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
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unsigned int sdp_transmit_line_num_deadline);
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bool dcn10_is_dig_enabled(struct link_encoder *enc);
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#endif /* __DC_LINK_ENCODER__DCN10_H__ */
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@ -38,7 +38,7 @@
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#include "dcn10/dcn10_hw_sequencer.h"
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#include "dce110/dce110_hw_sequencer.h"
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#include "dcn10/dcn10_opp.h"
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#include "dce/dce_link_encoder.h"
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#include "dcn10/dcn10_link_encoder.h"
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#include "dcn10/dcn10_stream_encoder.h"
|
||||
#include "dce/dce_clocks.h"
|
||||
#include "dce/dce_clock_source.h"
|
||||
|
|
@ -214,13 +214,11 @@ static const struct dce_aduio_mask audio_mask = {
|
|||
AUX_REG_LIST(id)\
|
||||
}
|
||||
|
||||
static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
|
||||
static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
|
||||
aux_regs(0),
|
||||
aux_regs(1),
|
||||
aux_regs(2),
|
||||
aux_regs(3),
|
||||
aux_regs(4),
|
||||
aux_regs(5)
|
||||
aux_regs(3)
|
||||
};
|
||||
|
||||
#define hpd_regs(id)\
|
||||
|
|
@ -228,13 +226,11 @@ static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
|
|||
HPD_REG_LIST(id)\
|
||||
}
|
||||
|
||||
static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
|
||||
static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
|
||||
hpd_regs(0),
|
||||
hpd_regs(1),
|
||||
hpd_regs(2),
|
||||
hpd_regs(3),
|
||||
hpd_regs(4),
|
||||
hpd_regs(5)
|
||||
hpd_regs(3)
|
||||
};
|
||||
|
||||
#define link_regs(id)\
|
||||
|
|
@ -243,14 +239,19 @@ static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
|
|||
SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
|
||||
}
|
||||
|
||||
static const struct dce110_link_enc_registers link_enc_regs[] = {
|
||||
static const struct dcn10_link_enc_registers link_enc_regs[] = {
|
||||
link_regs(0),
|
||||
link_regs(1),
|
||||
link_regs(2),
|
||||
link_regs(3),
|
||||
link_regs(4),
|
||||
link_regs(5),
|
||||
link_regs(6),
|
||||
link_regs(3)
|
||||
};
|
||||
|
||||
static const struct dcn10_link_enc_shift le_shift = {
|
||||
LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT)
|
||||
};
|
||||
|
||||
static const struct dcn10_link_enc_mask le_mask = {
|
||||
LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK)
|
||||
};
|
||||
|
||||
#define ipp_regs(id)\
|
||||
|
|
@ -583,20 +584,22 @@ static const struct encoder_feature_support link_enc_feature = {
|
|||
struct link_encoder *dcn10_link_encoder_create(
|
||||
const struct encoder_init_data *enc_init_data)
|
||||
{
|
||||
struct dce110_link_encoder *enc110 =
|
||||
kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
|
||||
struct dcn10_link_encoder *enc10 =
|
||||
kzalloc(sizeof(struct dcn10_link_encoder), GFP_KERNEL);
|
||||
|
||||
if (!enc110)
|
||||
if (!enc10)
|
||||
return NULL;
|
||||
|
||||
dce110_link_encoder_construct(enc110,
|
||||
dcn10_link_encoder_construct(enc10,
|
||||
enc_init_data,
|
||||
&link_enc_feature,
|
||||
&link_enc_regs[enc_init_data->transmitter],
|
||||
&link_enc_aux_regs[enc_init_data->channel - 1],
|
||||
&link_enc_hpd_regs[enc_init_data->hpd_source]);
|
||||
&link_enc_hpd_regs[enc_init_data->hpd_source],
|
||||
&le_shift,
|
||||
&le_mask);
|
||||
|
||||
return &enc110->base;
|
||||
return &enc10->base;
|
||||
}
|
||||
|
||||
struct clock_source *dcn10_clock_source_create(
|
||||
|
|
|
|||
Loading…
Reference in New Issue