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drm/amd/powerplay: correct code style 

Whitespace cleanup.

Signed-off-by: Jim Qu <Jim.Qu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jim Qu 2018-11-07 18:38:59 +08:00 committed by Alex Deucher
parent 9e834d7769
commit f0c9fabda1
1 changed files with 45 additions and 90 deletions
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135
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
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@ -3454,109 +3454,64 @@ static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
/* init/fini related */
.backend_init =
vega20_hwmgr_backend_init,
.backend_fini =
vega20_hwmgr_backend_fini,
.asic_setup =
vega20_setup_asic_task,
.power_off_asic =
vega20_power_off_asic,
.dynamic_state_management_enable =
vega20_enable_dpm_tasks,
.dynamic_state_management_disable =
vega20_disable_dpm_tasks,
.backend_init = vega20_hwmgr_backend_init,
.backend_fini = vega20_hwmgr_backend_fini,
.asic_setup = vega20_setup_asic_task,
.power_off_asic = vega20_power_off_asic,
.dynamic_state_management_enable = vega20_enable_dpm_tasks,
.dynamic_state_management_disable = vega20_disable_dpm_tasks,
/* power state related */
.apply_clocks_adjust_rules =
vega20_apply_clocks_adjust_rules,
.pre_display_config_changed =
vega20_pre_display_configuration_changed_task,
.display_config_changed =
vega20_display_configuration_changed_task,
.apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules,
.pre_display_config_changed = vega20_pre_display_configuration_changed_task,
.display_config_changed = vega20_display_configuration_changed_task,
.check_smc_update_required_for_display_configuration =
vega20_check_smc_update_required_for_display_configuration,
.notify_smc_display_config_after_ps_adjustment =
vega20_notify_smc_display_config_after_ps_adjustment,
/* export to DAL */
.get_sclk =
vega20_dpm_get_sclk,
.get_mclk =
vega20_dpm_get_mclk,
.get_dal_power_level =
vega20_get_dal_power_level,
.get_clock_by_type_with_latency =
vega20_get_clock_by_type_with_latency,
.get_clock_by_type_with_voltage =
vega20_get_clock_by_type_with_voltage,
.set_watermarks_for_clocks_ranges =
vega20_set_watermarks_for_clocks_ranges,
.display_clock_voltage_request =
vega20_display_clock_voltage_request,
.get_performance_level =
vega20_get_performance_level,
.get_sclk = vega20_dpm_get_sclk,
.get_mclk = vega20_dpm_get_mclk,
.get_dal_power_level = vega20_get_dal_power_level,
.get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
.get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage,
.set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges,
.display_clock_voltage_request = vega20_display_clock_voltage_request,
.get_performance_level = vega20_get_performance_level,
/* UMD pstate, profile related */
.force_dpm_level =
vega20_dpm_force_dpm_level,
.get_power_profile_mode =
vega20_get_power_profile_mode,
.set_power_profile_mode =
vega20_set_power_profile_mode,
.force_dpm_level = vega20_dpm_force_dpm_level,
.get_power_profile_mode = vega20_get_power_profile_mode,
.set_power_profile_mode = vega20_set_power_profile_mode,
/* od related */
.set_power_limit =
vega20_set_power_limit,
.get_sclk_od =
vega20_get_sclk_od,
.set_sclk_od =
vega20_set_sclk_od,
.get_mclk_od =
vega20_get_mclk_od,
.set_mclk_od =
vega20_set_mclk_od,
.odn_edit_dpm_table =
vega20_odn_edit_dpm_table,
.set_power_limit = vega20_set_power_limit,
.get_sclk_od = vega20_get_sclk_od,
.set_sclk_od = vega20_set_sclk_od,
.get_mclk_od = vega20_get_mclk_od,
.set_mclk_od = vega20_set_mclk_od,
.odn_edit_dpm_table = vega20_odn_edit_dpm_table,
/* for sysfs to retrive/set gfxclk/memclk */
.force_clock_level =
vega20_force_clock_level,
.print_clock_levels =
vega20_print_clock_levels,
.read_sensor =
vega20_read_sensor,
.force_clock_level = vega20_force_clock_level,
.print_clock_levels = vega20_print_clock_levels,
.read_sensor = vega20_read_sensor,
/* powergate related */
.powergate_uvd =
vega20_power_gate_uvd,
.powergate_vce =
vega20_power_gate_vce,
.powergate_uvd = vega20_power_gate_uvd,
.powergate_vce = vega20_power_gate_vce,
/* thermal related */
.start_thermal_controller =
vega20_start_thermal_controller,
.stop_thermal_controller =
vega20_thermal_stop_thermal_controller,
.get_thermal_temperature_range =
vega20_get_thermal_temperature_range,
.register_irq_handlers =
smu9_register_irq_handlers,
.disable_smc_firmware_ctf =
vega20_thermal_disable_alert,
.start_thermal_controller = vega20_start_thermal_controller,
.stop_thermal_controller = vega20_thermal_stop_thermal_controller,
.get_thermal_temperature_range = vega20_get_thermal_temperature_range,
.register_irq_handlers = smu9_register_irq_handlers,
.disable_smc_firmware_ctf = vega20_thermal_disable_alert,
/* fan control related */
.get_fan_speed_percent =
vega20_fan_ctrl_get_fan_speed_percent,
.set_fan_speed_percent =
vega20_fan_ctrl_set_fan_speed_percent,
.get_fan_speed_info =
vega20_fan_ctrl_get_fan_speed_info,
.get_fan_speed_rpm =
vega20_fan_ctrl_get_fan_speed_rpm,
.set_fan_speed_rpm =
vega20_fan_ctrl_set_fan_speed_rpm,
.get_fan_control_mode =
vega20_get_fan_control_mode,
.set_fan_control_mode =
vega20_set_fan_control_mode,
.get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent,
.set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent,
.get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info,
.get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm,
.set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm,
.get_fan_control_mode = vega20_get_fan_control_mode,
.set_fan_control_mode = vega20_set_fan_control_mode,
/* smu memory related */
.notify_cac_buffer_info =
vega20_notify_cac_buffer_info,
.enable_mgpu_fan_boost =
vega20_enable_mgpu_fan_boost,
.notify_cac_buffer_info = vega20_notify_cac_buffer_info,
.enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost,
};
int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)