MIPS: retire "asm/llsc.h"
all that "asm/llsc.h" does is just to help inline asm, which can be stringifyed from "asm/asm.h" +. Since "asm/asm.h" has all we need, retire "asm/llsc.h" +. remove unused header file Inspired-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Huang Pei <huangpei@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Huang Pei
Thomas Bogendoerfer
parent
10657660c1
commit
f0b7ddbd79
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@ -222,6 +222,8 @@ symbol = value
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#define LONG_SRLV srlv
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#define LONG_SRA sra
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#define LONG_SRAV srav
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#define LONG_INS ins
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#define LONG_EXT ext
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#ifdef __ASSEMBLY__
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#define LONG .word
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@ -249,6 +251,8 @@ symbol = value
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#define LONG_SRLV dsrlv
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#define LONG_SRA dsra
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#define LONG_SRAV dsrav
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#define LONG_INS dins
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#define LONG_EXT dext
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#ifdef __ASSEMBLY__
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#define LONG .dword
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@ -16,13 +16,12 @@
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#include <linux/irqflags.h>
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#include <linux/types.h>
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#include <asm/asm.h>
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#include <asm/barrier.h>
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#include <asm/compiler.h>
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#include <asm/cpu-features.h>
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#include <asm/cmpxchg.h>
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#include <asm/llsc.h>
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#include <asm/sync.h>
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#include <asm/war.h>
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#define ATOMIC_OPS(pfx, type) \
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static __always_inline type arch_##pfx##_read(const pfx##_t *v) \
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@ -74,7 +73,7 @@ static __inline__ void arch_##pfx##_##op(type i, pfx##_t * v) \
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"1: " #ll " %0, %1 # " #pfx "_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" " #sc " %0, %1 \n" \
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"\t" __SC_BEQZ "%0, 1b \n" \
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"\t" __stringify(SC_BEQZ) " %0, 1b \n" \
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" .set pop \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i) : __LLSC_CLOBBER); \
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@ -104,7 +103,7 @@ arch_##pfx##_##op##_return_relaxed(type i, pfx##_t * v) \
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"1: " #ll " %1, %2 # " #pfx "_" #op "_return\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" " #sc " %0, %2 \n" \
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"\t" __SC_BEQZ "%0, 1b \n" \
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"\t" __stringify(SC_BEQZ) " %0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set pop \n" \
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: "=&r" (result), "=&r" (temp), \
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@ -137,7 +136,7 @@ arch_##pfx##_fetch_##op##_relaxed(type i, pfx##_t * v) \
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"1: " #ll " %1, %2 # " #pfx "_fetch_" #op "\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" " #sc " %0, %2 \n" \
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"\t" __SC_BEQZ "%0, 1b \n" \
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"\t" __stringify(SC_BEQZ) " %0, 1b \n" \
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" .set pop \n" \
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" move %0, %1 \n" \
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: "=&r" (result), "=&r" (temp), \
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@ -237,7 +236,7 @@ static __inline__ type arch_##pfx##_sub_if_positive(type i, pfx##_t * v) \
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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" " #sc " %1, %2 \n" \
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" " __SC_BEQZ "%1, 1b \n" \
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" " __stringify(SC_BEQZ) " %1, 1b \n" \
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"2: " __SYNC(full, loongson3_war) " \n" \
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" .set pop \n" \
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: "=&r" (result), "=&r" (temp), \
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@ -16,14 +16,12 @@
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#include <linux/bits.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/asm.h>
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#include <asm/barrier.h>
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#include <asm/byteorder.h> /* sigh ... */
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#include <asm/compiler.h>
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#include <asm/cpu-features.h>
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#include <asm/isa-rev.h>
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#include <asm/llsc.h>
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#include <asm/sgidefs.h>
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#include <asm/war.h>
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#define __bit_op(mem, insn, inputs...) do { \
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unsigned long __temp; \
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@ -32,10 +30,10 @@
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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" " __SYNC(full, loongson3_war) " \n" \
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"1: " __LL "%0, %1 \n" \
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"1: " __stringify(LONG_LL) " %0, %1 \n" \
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" " insn " \n" \
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" " __SC "%0, %1 \n" \
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" " __SC_BEQZ "%0, 1b \n" \
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" " __stringify(LONG_SC) " %0, %1 \n" \
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" " __stringify(SC_BEQZ) " %0, 1b \n" \
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" .set pop \n" \
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: "=&r"(__temp), "+" GCC_OFF_SMALL_ASM()(mem) \
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: inputs \
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@ -49,10 +47,10 @@
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" .set push \n" \
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" .set " MIPS_ISA_LEVEL " \n" \
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" " __SYNC(full, loongson3_war) " \n" \
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"1: " __LL ll_dst ", %2 \n" \
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"1: " __stringify(LONG_LL) " " ll_dst ", %2\n" \
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" " insn " \n" \
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" " __SC "%1, %2 \n" \
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" " __SC_BEQZ "%1, 1b \n" \
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" " __stringify(LONG_SC) " %1, %2 \n" \
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" " __stringify(SC_BEQZ) " %1, 1b \n" \
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" .set pop \n" \
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: "=&r"(__orig), "=&r"(__temp), \
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"+" GCC_OFF_SMALL_ASM()(mem) \
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@ -98,7 +96,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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}
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if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit) && (bit >= 16)) {
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__bit_op(*m, __INS "%0, %3, %2, 1", "i"(bit), "r"(~0));
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__bit_op(*m, __stringify(LONG_INS) " %0, %3, %2, 1", "i"(bit), "r"(~0));
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return;
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}
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@ -126,7 +124,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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}
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if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(bit)) {
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__bit_op(*m, __INS "%0, $0, %2, 1", "i"(bit));
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__bit_op(*m, __stringify(LONG_INS) " %0, $0, %2, 1", "i"(bit));
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return;
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}
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@ -234,8 +232,8 @@ static inline int test_and_clear_bit(unsigned long nr,
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res = __mips_test_and_clear_bit(nr, addr);
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} else if ((MIPS_ISA_REV >= 2) && __builtin_constant_p(nr)) {
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res = __test_bit_op(*m, "%1",
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__EXT "%0, %1, %3, 1;"
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__INS "%1, $0, %3, 1",
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__stringify(LONG_EXT) " %0, %1, %3, 1;"
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__stringify(LONG_INS) " %1, $0, %3, 1",
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"i"(bit));
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} else {
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orig = __test_bit_op(*m, "%0",
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@ -10,10 +10,9 @@
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#include <linux/bug.h>
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#include <linux/irqflags.h>
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#include <asm/asm.h>
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#include <asm/compiler.h>
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#include <asm/llsc.h>
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#include <asm/sync.h>
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#include <asm/war.h>
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/*
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* These functions doesn't exist, so if they are called you'll either:
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@ -48,7 +47,7 @@ extern unsigned long __xchg_called_with_bad_pointer(void)
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" move $1, %z3 \n" \
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" .set " MIPS_ISA_ARCH_LEVEL " \n" \
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" " st " $1, %1 \n" \
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"\t" __SC_BEQZ "$1, 1b \n" \
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"\t" __stringify(SC_BEQZ) " $1, 1b \n" \
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" .set pop \n" \
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: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
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: GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \
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@ -127,7 +126,7 @@ unsigned long __xchg(volatile void *ptr, unsigned long x, int size)
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" move $1, %z4 \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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" " st " $1, %1 \n" \
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"\t" __SC_BEQZ "$1, 1b \n" \
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"\t" __stringify(SC_BEQZ) " $1, 1b \n" \
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" .set pop \n" \
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"2: " __SYNC(full, loongson3_war) " \n" \
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: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m) \
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@ -282,7 +281,7 @@ static inline unsigned long __cmpxchg64(volatile void *ptr,
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/* Attempt to store new at ptr */
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" scd %L1, %2 \n"
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/* If we failed, loop! */
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"\t" __SC_BEQZ "%L1, 1b \n"
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"\t" __stringify(SC_BEQZ) " %L1, 1b \n"
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"2: " __SYNC(full, loongson3_war) " \n"
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" .set pop \n"
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: "=&r"(ret),
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@ -20,6 +20,7 @@
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#include <linux/threads.h>
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#include <linux/spinlock.h>
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#include <asm/asm.h>
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#include <asm/inst.h>
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#include <asm/mipsregs.h>
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@ -379,9 +380,9 @@ static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
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__asm__ __volatile__(
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" .set push \n"
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" .set "MIPS_ISA_ARCH_LEVEL" \n"
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" " __LL "%0, %1 \n"
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" "__stringify(LONG_LL) " %0, %1 \n"
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" or %0, %2 \n"
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" " __SC "%0, %1 \n"
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" "__stringify(LONG_SC) " %0, %1 \n"
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" .set pop \n"
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: "=&r" (temp), "+m" (*reg)
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: "r" (val));
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@ -396,9 +397,9 @@ static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
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__asm__ __volatile__(
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" .set push \n"
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" .set "MIPS_ISA_ARCH_LEVEL" \n"
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" " __LL "%0, %1 \n"
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" "__stringify(LONG_LL) " %0, %1 \n"
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" and %0, %2 \n"
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" " __SC "%0, %1 \n"
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" "__stringify(LONG_SC) " %0, %1 \n"
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" .set pop \n"
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: "=&r" (temp), "+m" (*reg)
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: "r" (~val));
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@ -414,10 +415,10 @@ static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
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__asm__ __volatile__(
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" .set push \n"
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" .set "MIPS_ISA_ARCH_LEVEL" \n"
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" " __LL "%0, %1 \n"
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" "__stringify(LONG_LL) " %0, %1 \n"
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" and %0, %2 \n"
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" or %0, %3 \n"
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" " __SC "%0, %1 \n"
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" "__stringify(LONG_SC) " %0, %1 \n"
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" .set pop \n"
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: "=&r" (temp), "+m" (*reg)
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: "r" (~change), "r" (val & change));
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@ -1,39 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Macros for 32/64-bit neutral inline assembler
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*/
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#ifndef __ASM_LLSC_H
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#define __ASM_LLSC_H
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#include <asm/isa-rev.h>
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#if _MIPS_SZLONG == 32
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#define __LL "ll "
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#define __SC "sc "
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#define __INS "ins "
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#define __EXT "ext "
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#elif _MIPS_SZLONG == 64
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#define __LL "lld "
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#define __SC "scd "
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#define __INS "dins "
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#define __EXT "dext "
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#endif
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/*
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* Using a branch-likely instruction to check the result of an sc instruction
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* works around a bug present in R10000 CPUs prior to revision 3.0 that could
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* cause ll-sc sequences to execute non-atomically.
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*/
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#ifdef CONFIG_WAR_R10000_LLSC
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# define __SC_BEQZ "beqzl "
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#elif MIPS_ISA_REV >= 6
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# define __SC_BEQZ "beqzc "
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#else
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# define __SC_BEQZ "beqz "
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#endif
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#endif /* __ASM_LLSC_H */
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