drm/i915: Enable register whitelist checks
MI_STORE_REGISTER_MEM, MI_LOAD_REGISTER_MEM, and MI_LOAD_REGISTER_IMM commands allow userspace access to registers. Only certain registers should be allowed for such access, so enable checking for those commands. Each ring gets its own register whitelist. MI_LOAD_REGISTER_REG on HSW also allows register access but is currently unused by userspace components. Leave it rejected. PIPE_CONTROL and MEDIA_VFE_STATE allow register access based on certain bits being set. Reject those as well. v2: trailing commas, rebased OTC-Tracker: AXIA-4631 Change-Id: Ie614a2f0eb2e5917de809e5a17957175d24cc44f Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -122,9 +122,12 @@ static const struct drm_i915_cmd_descriptor common_cmds[] = {
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CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ),
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CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ),
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CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ),
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CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, R ),
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CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, R ),
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CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, R ),
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CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
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.reg = { .offset = 1, .mask = 0x007FFFFC } ),
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CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W,
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.reg = { .offset = 1, .mask = 0x007FFFFC } ),
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CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W,
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.reg = { .offset = 1, .mask = 0x007FFFFC } ),
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CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ),
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};
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@ -141,9 +144,21 @@ static const struct drm_i915_cmd_descriptor render_cmds[] = {
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CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, S ),
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CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ),
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CMD( PIPELINE_SELECT, S3D, F, 1, S ),
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CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B,
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.bits = {{
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.offset = 2,
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.mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
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.expected = 0,
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}}, ),
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CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ),
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CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ),
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CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ),
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CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,
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.bits = {{
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.offset = 1,
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.mask = PIPE_CONTROL_MMIO_WRITE,
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.expected = 0,
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}}, ),
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};
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static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
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@ -331,6 +331,7 @@
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#define DISPLAY_PLANE_B (1<<20)
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#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
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#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
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#define PIPE_CONTROL_MMIO_WRITE (1<<23)
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#define PIPE_CONTROL_CS_STALL (1<<20)
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#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
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#define PIPE_CONTROL_QW_WRITE (1<<14)
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@ -371,6 +372,8 @@
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#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
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#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
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#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
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#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
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#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
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#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
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#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
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