arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes
Adds the core gpu, and dsi nodes for the apq8064 needed to get graphics working on the nexus7 and other devices. These apply on top of Archit's patch set that enables HDMI for IFC6410 Feedback would be greatly appreciated! Cc: Archit Taneja <architt@codeaurora.org> Cc: vinay simha <vinaysimha@inforcecomputing.com> Cc: andy.gross@linaro.org Cc: robdclark@gmail.com Cc: linux-arm-msm@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
John Stultz
Andy Gross
parent
c809801d4c
commit
f078eac68e
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@ -1060,6 +1060,231 @@
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reg = <0x1a400000 0x100>;
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};
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gpu: adreno-3xx@4300000 {
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compatible = "qcom,adreno-3xx";
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reg = <0x04300000 0x20000>;
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reg-names = "kgsl_3d0_reg_memory";
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interrupts = <GIC_SPI 80 0>;
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interrupt-names = "kgsl_3d0_irq";
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clock-names =
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"core_clk",
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"iface_clk",
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"mem_clk",
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"mem_iface_clk";
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clocks =
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<&mmcc GFX3D_CLK>,
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<&mmcc GFX3D_AHB_CLK>,
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<&mmcc GFX3D_AXI_CLK>,
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<&mmcc MMSS_IMEM_AHB_CLK>;
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qcom,chipid = <0x03020002>;
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iommus = <&gfx3d 0
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&gfx3d 1
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&gfx3d 2
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&gfx3d 3
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&gfx3d 4
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&gfx3d 5
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&gfx3d 6
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&gfx3d 7
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&gfx3d 8
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&gfx3d 9
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&gfx3d 10
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&gfx3d 11
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&gfx3d 12
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&gfx3d 13
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&gfx3d 14
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&gfx3d 15
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&gfx3d 16
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&gfx3d 17
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&gfx3d 18
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&gfx3d 19
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&gfx3d 20
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&gfx3d 21
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&gfx3d 22
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&gfx3d 23
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&gfx3d 24
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&gfx3d 25
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&gfx3d 26
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&gfx3d 27
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&gfx3d 28
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&gfx3d 29
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&gfx3d 30
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&gfx3d 31
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&gfx3d1 0
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&gfx3d1 1
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&gfx3d1 2
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&gfx3d1 3
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&gfx3d1 4
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&gfx3d1 5
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&gfx3d1 6
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&gfx3d1 7
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&gfx3d1 8
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&gfx3d1 9
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&gfx3d1 10
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&gfx3d1 11
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&gfx3d1 12
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&gfx3d1 13
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&gfx3d1 14
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&gfx3d1 15
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&gfx3d1 16
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&gfx3d1 17
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&gfx3d1 18
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&gfx3d1 19
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&gfx3d1 20
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&gfx3d1 21
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&gfx3d1 22
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&gfx3d1 23
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&gfx3d1 24
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&gfx3d1 25
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&gfx3d1 26
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&gfx3d1 27
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&gfx3d1 28
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&gfx3d1 29
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&gfx3d1 30
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&gfx3d1 31>;
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qcom,gpu-pwrlevels {
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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qcom,gpu-freq = <450000000>;
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};
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qcom,gpu-pwrlevel@1 {
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qcom,gpu-freq = <27000000>;
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};
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};
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};
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mmss_sfpb: syscon@5700000 {
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compatible = "syscon";
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reg = <0x5700000 0x70>;
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};
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dsi0: mdss_dsi@4700000 {
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compatible = "qcom,mdss-dsi-ctrl";
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label = "MDSS DSI CTRL->0";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 82 0>;
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reg = <0x04700000 0x200>;
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reg-names = "dsi_ctrl";
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clocks = <&mmcc DSI_M_AHB_CLK>,
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<&mmcc DSI_S_AHB_CLK>,
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<&mmcc AMP_AHB_CLK>,
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<&mmcc DSI_CLK>,
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<&mmcc DSI1_BYTE_CLK>,
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<&mmcc DSI_PIXEL_CLK>,
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<&mmcc DSI1_ESC_CLK>;
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clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
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"src_clk", "byte_clk", "pixel_clk",
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"core_clk";
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assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
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<&mmcc DSI1_ESC_SRC>,
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<&mmcc DSI_SRC>,
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<&mmcc DSI_PIXEL_SRC>;
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assigned-clock-parents = <&dsi0_phy 0>,
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<&dsi0_phy 0>,
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<&dsi0_phy 1>,
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<&dsi0_phy 1>;
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syscon-sfpb = <&mmss_sfpb>;
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phys = <&dsi0_phy>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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};
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};
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};
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};
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dsi0_phy: dsi-phy@4700200 {
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compatible = "qcom,dsi-phy-28nm-8960";
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#clock-cells = <1>;
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reg = <0x04700200 0x100>,
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<0x04700300 0x200>,
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<0x04700500 0x5c>;
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reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
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clock-names = "iface_clk";
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clocks = <&mmcc DSI_M_AHB_CLK>;
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};
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mdp_port0: iommu@7500000 {
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compatible = "qcom,apq8064-iommu";
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#iommu-cells = <1>;
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clock-names =
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"smmu_pclk",
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"iommu_clk";
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clocks =
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<&mmcc SMMU_AHB_CLK>,
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<&mmcc MDP_AXI_CLK>;
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reg = <0x07500000 0x100000>;
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interrupts =
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<GIC_SPI 63 0>,
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<GIC_SPI 64 0>;
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qcom,ncb = <2>;
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};
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mdp_port1: iommu@7600000 {
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compatible = "qcom,apq8064-iommu";
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#iommu-cells = <1>;
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clock-names =
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"smmu_pclk",
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"iommu_clk";
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clocks =
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<&mmcc SMMU_AHB_CLK>,
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<&mmcc MDP_AXI_CLK>;
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reg = <0x07600000 0x100000>;
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interrupts =
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<GIC_SPI 61 0>,
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<GIC_SPI 62 0>;
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qcom,ncb = <2>;
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};
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gfx3d: iommu@7c00000 {
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compatible = "qcom,apq8064-iommu";
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#iommu-cells = <1>;
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clock-names =
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"smmu_pclk",
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"iommu_clk";
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clocks =
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<&mmcc SMMU_AHB_CLK>,
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<&mmcc GFX3D_AXI_CLK>;
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reg = <0x07c00000 0x100000>;
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interrupts =
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<GIC_SPI 69 0>,
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<GIC_SPI 70 0>;
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qcom,ncb = <3>;
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};
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gfx3d1: iommu@7d00000 {
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compatible = "qcom,apq8064-iommu";
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#iommu-cells = <1>;
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clock-names =
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"smmu_pclk",
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"iommu_clk";
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clocks =
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<&mmcc SMMU_AHB_CLK>,
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<&mmcc GFX3D_AXI_CLK>;
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reg = <0x07d00000 0x100000>;
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interrupts =
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<GIC_SPI 210 0>,
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<GIC_SPI 211 0>;
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qcom,ncb = <3>;
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};
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pcie: pci@1b500000 {
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compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
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reg = <0x1b500000 0x1000
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@ -1157,6 +1382,11 @@
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"hdmi_clk",
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"tv_clk";
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iommus = <&mdp_port0 0
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&mdp_port0 2
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&mdp_port1 0
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&mdp_port1 2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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