mmsys:
- add SW reset to MT8192 - add support for MT8195 pmic wrapper: - update binding description needed for future MT8195 support mutex: - add support for MT8195 cmdq helper: - remove legacy callback -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmJ+De4XHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQL21+TfbCqH5NixAAmtUXQou9YAIrg42JtqjkiwlL Nub1G2cQSRVKI+H3sSvLbN8oqYBLggV9sbgrJ1CTaMTOun+fmFMujr9noRDl+Rv0 ZpaU0sVqOgGeuoiHJb6vH9wifzH34ZIKNEazZpQAO+PbufidbCXWFTTLbWjW2fSK b2yf5X6gXj7ZxaG0e7ByUguDIjZCGaVl0z5DaQcoczCFTLglwDozCiRPRc37s6MZ Hlh6flrlP2Z/hkLQ21uk6zAq2qy87br9AOW91rcAghtNyq0gkHwnyYM4sh00IqOz FN6Z7V1kWe/el1RA6Fm02+8QMYf7ZIv1DwR10L1isqG3o2KpNjRVpesIzMsr2DlW 2m58rmip5P662YYZ2dXQtmqK2rW1mn7XjRslOtTYPRPD637fe3g1J/a/bcVqWiOy 8eYNxIRw3uQVKjaNwca6CXW1iRugyMj235RtN6vxiAcvj48CMctqlP+9vRQGfAat L1yDj13/NpeiXI5VlBKg/j4s2ed/WH7SeQO9RUHzJtuiR/VjtTKX2E7CNN3XkA6O U93AJ6qJ6RQYpZ/I79dnM8F/ZI5GQyCePl6qgomNrLIVQw284ZcNcMpu0jY7krX3 GE8m7T36qs3a4mQyKHTjpl6GOtfInIV9usGEjW8DYkvIpN5UfVsRmaNVgVMX6or+ BEBhVdy7/0NYHHclDhM= =bP/W -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmJ+S1IACgkQmmx57+YA GNnVUxAAtkqUi1+cHK7ms86WMTskd1JgLOc21SBYQCC7YTJkEadu/Fk2+Jx3r66w SVHa3wXkrSGephW7o8uHurD7MnI3dunfvvzFKpcfGAH8nh5stdQs28E14km8O00G n0rUQ2CvhLNehGaY4D/EnefAIMvCV6dB3XNfpLj7QqHFIImVDTmMqFl+dtu1FUr9 lHxeBmNSsxD+GJ8AFoPOWq9k3JKSXgbFv97WRTt9SodfMRdqz0yX6LTvS0qb+nQ7 SLftnHxRtlD1D4HSU0g7LlftQ587hfrcf7YLWfuKtG6CElnz7fE/NpZ+2PLC1rDC MQKySJfQ1Zhqb1TdrgTDxBicnNDmGGVH3uWzyq/4XvRO9PByLVLoX6Zzj92wpdpD erK8q1uFd5CawmwlhPfTEcySesfhd3jcW5BJ7m+1gp5iYZw64HPwf9K/UuOK/chJ a1mbxz1eDn/kEOOukYoxJFoyOM1JSy1kljik0bj9X6PNrEsdVGSJQrlDz6MQMSzJ O95+a0steBxzi3ZYJ7g0R72qWVQEF8qCJoEb1WXNrIWOtWSVrxt+UbBODZoBtpc9 Gh4rjEwne6P62kZBMQVxBGzXQMlUT3zYz6S900s7jx3kNXgtX6BTxTi5mphmhPhj 2HdDg+RUysmGbEi98O1iuaXO5J7bffwuJP4poC8vOaQ359BAop4= =j3GJ -----END PGP SIGNATURE----- Merge tag 'v5.18-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/soc mmsys: - add SW reset to MT8192 - add support for MT8195 pmic wrapper: - update binding description needed for future MT8195 support mutex: - add support for MT8195 cmdq helper: - remove legacy callback * tag 'v5.18-next-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: soc: mediatek: mutex: remove mt8195 MOD0 and SOF0 definition dt-bindings: pwrap: mediatek: Update pwrap document for mt8195 soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0 soc: mediatek: add mtk-mutex support for mt8195 vdosys0 soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 soc: mediatek: cmdq: Use mailbox rx_callback instead of cmdq_task_cb dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding dt-bindings: arm: mediatek: mmsys: add power and gce properties soc: mediatek: mmsys: Add sw0_rst_offset for MT8192 Link: https://lore.kernel.org/r/6412eecf-a4c3-cf06-55ff-9df8b0656d21@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
f03e95098e
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@ -31,6 +31,7 @@ properties:
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- mediatek,mt8183-mmsys
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- mediatek,mt8186-mmsys
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- mediatek,mt8192-mmsys
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- mediatek,mt8195-mmsys
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- mediatek,mt8365-mmsys
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- const: syscon
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- items:
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@ -41,6 +42,30 @@ properties:
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reg:
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maxItems: 1
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power-domains:
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description:
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A phandle and PM domain specifier as defined by bindings
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of the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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mboxes:
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description:
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Using mailbox to communicate with GCE, it should have this
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property and list of phandle, mailbox specifiers. See
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Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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mediatek,gce-client-reg:
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description:
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The register of client driver can be configured by gce with 4 arguments
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defined in this property, such as phandle of gce, subsys id,
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register offset and size.
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Each subsys id is mapping to a base address of display function blocks
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register which is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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"#clock-cells":
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const: 1
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@ -56,9 +81,16 @@ additionalProperties: false
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examples:
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- |
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#include <dt-bindings/power/mt8173-power.h>
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#include <dt-bindings/gce/mt8173-gce.h>
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt8173-mmsys", "syscon";
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reg = <0x14000000 0x1000>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
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<&gce 1 CMDQ_THR_PRIO_HIGHEST>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
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};
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@ -31,20 +31,20 @@ Required properties in pwrap device node.
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"mediatek,mt8195-pwrap" for MT8195 SoCs
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"mediatek,mt8516-pwrap" for MT8516 SoCs
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- interrupts: IRQ for pwrap in SOC
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- reg-names: Must include the following entries:
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- reg-names: "pwrap" is required; "pwrap-bridge" is optional.
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"pwrap": Main registers base
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"pwrap-bridge": bridge base (IP Pairing)
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- reg: Must contain an entry for each entry in reg-names.
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- reset-names: Must include the following entries:
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"pwrap"
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"pwrap-bridge" (IP Pairing)
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- resets: Must contain an entry for each entry in reset-names.
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- clock-names: Must include the following entries:
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"spi": SPI bus clock
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"wrap": Main module clock
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- clocks: Must contain an entry for each entry in clock-names.
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Optional properities:
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- reset-names: Some SoCs include the following entries:
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"pwrap"
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"pwrap-bridge" (IP Pairing)
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- resets: Must contain an entry for each entry in reset-names.
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- pmic: Using either MediaTek PMIC MFD as the child device of pwrap
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See the following for child node definitions:
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Documentation/devicetree/bindings/mfd/mt6397.txt
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@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
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MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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|
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@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
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MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
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MT8183_OVL1_2L_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
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MT8183_DITHER0_MOUT_IN_DSI0
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}, {
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@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
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MT8186_RDMA0_SOUT_TO_COLOR0
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},
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{
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
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MT8186_DITHER0_MOUT_TO_DSI0,
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},
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{
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
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MT8186_DSI0_FROM_DITHER0
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},
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@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
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MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
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MT8192_OVL2_2L_MOUT_EN_RDMA4
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
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MT8192_DITHER0_MOUT_IN_DSI0
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}, {
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@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
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MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
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MT8192_AAL0_SEL_IN_CCORR0
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}, {
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DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
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MT8192_DSI0_SEL_IN_DITHER0
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}, {
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@ -0,0 +1,370 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
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#define __SOC_MEDIATEK_MT8195_MMSYS_H
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#define MT8195_VDO0_OVL_MOUT_EN 0xf14
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#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
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#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
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#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
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#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
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#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
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#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
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#define MT8195_VDO0_SEL_IN 0xf34
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#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
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#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
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#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
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#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
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#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
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#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
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#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
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#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
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#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
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#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
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#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
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#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
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#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
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#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
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#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
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#define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
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#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
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#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
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#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
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#define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
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#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
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#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
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#define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
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#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
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#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
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#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
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#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
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#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
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#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
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#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
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#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
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#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
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#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
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#define MT8195_VDO0_SEL_OUT 0xf38
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#define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
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#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
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#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
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#define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
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#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
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#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
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#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
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#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
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#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
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#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
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#define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
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#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
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#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
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#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
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#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
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#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
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#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
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#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
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static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
|
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
|
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
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MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
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}, {
|
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DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
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MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
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MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
|
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}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
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MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
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MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
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MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
|
||||
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
|
||||
MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
|
||||
MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
|
||||
MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
|
||||
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
|
||||
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
|
||||
MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
|
||||
MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
|
||||
MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
|
||||
MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
|
||||
MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
|
||||
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
|
||||
}, {
|
||||
DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
|
||||
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
|
||||
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER0_TO_DSI0
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
|
||||
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
|
||||
MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
|
||||
MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DSI1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
|
||||
}, {
|
||||
DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
|
||||
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
|
||||
}, {
|
||||
DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
|
||||
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
|
||||
MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
|
|
@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
|
|||
MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
|
||||
},
|
||||
{
|
||||
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
|
||||
MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
|
||||
},
|
||||
{
|
||||
DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
|
||||
DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
|
||||
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
|
||||
MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
|
||||
},
|
||||
|
|
|
@ -425,34 +425,11 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
|
|||
}
|
||||
EXPORT_SYMBOL(cmdq_pkt_finalize);
|
||||
|
||||
static void cmdq_pkt_flush_async_cb(struct cmdq_cb_data data)
|
||||
{
|
||||
struct cmdq_pkt *pkt = (struct cmdq_pkt *)data.data;
|
||||
struct cmdq_task_cb *cb = &pkt->cb;
|
||||
struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
|
||||
|
||||
dma_sync_single_for_cpu(client->chan->mbox->dev, pkt->pa_base,
|
||||
pkt->cmd_buf_size, DMA_TO_DEVICE);
|
||||
if (cb->cb) {
|
||||
data.data = cb->data;
|
||||
cb->cb(data);
|
||||
}
|
||||
}
|
||||
|
||||
int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
|
||||
void *data)
|
||||
int cmdq_pkt_flush_async(struct cmdq_pkt *pkt)
|
||||
{
|
||||
int err;
|
||||
struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
|
||||
|
||||
pkt->cb.cb = cb;
|
||||
pkt->cb.data = data;
|
||||
pkt->async_cb.cb = cmdq_pkt_flush_async_cb;
|
||||
pkt->async_cb.data = pkt;
|
||||
|
||||
dma_sync_single_for_device(client->chan->mbox->dev, pkt->pa_base,
|
||||
pkt->cmd_buf_size, DMA_TO_DEVICE);
|
||||
|
||||
err = mbox_send_message(client->chan, pkt);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include "mt8183-mmsys.h"
|
||||
#include "mt8186-mmsys.h"
|
||||
#include "mt8192-mmsys.h"
|
||||
#include "mt8195-mmsys.h"
|
||||
#include "mt8365-mmsys.h"
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
|
||||
|
@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
|
|||
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt2701_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt2712-mm",
|
||||
.routes = mmsys_default_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt2712_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt6779-mm",
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt6779_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt6797-mm",
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt6797_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt8167-mm",
|
||||
.routes = mt8167_mmsys_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt8167_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt8173-mm",
|
||||
.routes = mmsys_default_routing_table,
|
||||
|
@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
|
|||
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt8173_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt8183-mm",
|
||||
.routes = mmsys_mt8183_routing_table,
|
||||
|
@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
|
|||
.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt8183_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt8186-mm",
|
||||
.routes = mmsys_mt8186_routing_table,
|
||||
|
@ -66,10 +116,45 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
|
|||
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt8186_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
|
||||
.clk_driver = "clk-mt8192-mm",
|
||||
.routes = mmsys_mt8192_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
|
||||
.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt8192_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
|
||||
.io_start = 0x1c01a000,
|
||||
.clk_driver = "clk-mt8195-vdo0",
|
||||
.routes = mmsys_mt8195_routing_table,
|
||||
.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
|
||||
.io_start = 0x1c100000,
|
||||
.clk_driver = "clk-mt8195-vdo1",
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
|
||||
.num_drv_data = 2,
|
||||
.drv_data = {
|
||||
&mt8195_vdosys0_driver_data,
|
||||
&mt8195_vdosys1_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
|
||||
|
@ -78,13 +163,33 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
|
|||
.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
|
||||
};
|
||||
|
||||
static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
|
||||
.num_drv_data = 1,
|
||||
.drv_data = {
|
||||
&mt8365_mmsys_driver_data,
|
||||
},
|
||||
};
|
||||
|
||||
struct mtk_mmsys {
|
||||
void __iomem *regs;
|
||||
const struct mtk_mmsys_driver_data *data;
|
||||
spinlock_t lock; /* protects mmsys_sw_rst_b reg */
|
||||
struct reset_controller_dev rcdev;
|
||||
phys_addr_t io_start;
|
||||
};
|
||||
|
||||
static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
|
||||
const struct mtk_mmsys_match_data *match)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < match->num_drv_data; i++)
|
||||
if (mmsys->io_start == match->drv_data[i]->io_start)
|
||||
return i;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
void mtk_mmsys_ddp_connect(struct device *dev,
|
||||
enum mtk_ddp_comp_id cur,
|
||||
enum mtk_ddp_comp_id next)
|
||||
|
@ -179,7 +284,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
|
|||
struct device *dev = &pdev->dev;
|
||||
struct platform_device *clks;
|
||||
struct platform_device *drm;
|
||||
const struct mtk_mmsys_match_data *match_data;
|
||||
struct mtk_mmsys *mmsys;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
|
||||
|
@ -205,7 +312,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
mmsys->data = of_device_get_match_data(&pdev->dev);
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(dev, "Couldn't get mmsys resource\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
mmsys->io_start = res->start;
|
||||
|
||||
match_data = of_device_get_match_data(dev);
|
||||
if (match_data->num_drv_data > 1) {
|
||||
/* This SoC has multiple mmsys channels */
|
||||
ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Couldn't get match driver data\n");
|
||||
return ret;
|
||||
}
|
||||
mmsys->data = match_data->drv_data[ret];
|
||||
} else {
|
||||
dev_dbg(dev, "Using single mmsys channel\n");
|
||||
mmsys->data = match_data->drv_data[0];
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, mmsys);
|
||||
|
||||
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
|
||||
|
@ -226,43 +353,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
|
|||
static const struct of_device_id of_match_mtk_mmsys[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt2701-mmsys",
|
||||
.data = &mt2701_mmsys_driver_data,
|
||||
.data = &mt2701_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt2712-mmsys",
|
||||
.data = &mt2712_mmsys_driver_data,
|
||||
.data = &mt2712_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt6779-mmsys",
|
||||
.data = &mt6779_mmsys_driver_data,
|
||||
.data = &mt6779_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt6797-mmsys",
|
||||
.data = &mt6797_mmsys_driver_data,
|
||||
.data = &mt6797_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8167-mmsys",
|
||||
.data = &mt8167_mmsys_driver_data,
|
||||
.data = &mt8167_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8173-mmsys",
|
||||
.data = &mt8173_mmsys_driver_data,
|
||||
.data = &mt8173_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8183-mmsys",
|
||||
.data = &mt8183_mmsys_driver_data,
|
||||
.data = &mt8183_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8186-mmsys",
|
||||
.data = &mt8186_mmsys_driver_data,
|
||||
.data = &mt8186_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8192-mmsys",
|
||||
.data = &mt8192_mmsys_driver_data,
|
||||
.data = &mt8192_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8195-mmsys",
|
||||
.data = &mt8195_mmsys_match_data,
|
||||
},
|
||||
{
|
||||
.compatible = "mediatek,mt8365-mmsys",
|
||||
.data = &mt8365_mmsys_driver_data,
|
||||
.data = &mt8365_mmsys_match_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
|
|
@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
|
|||
};
|
||||
|
||||
struct mtk_mmsys_driver_data {
|
||||
const resource_size_t io_start;
|
||||
const char *clk_driver;
|
||||
const struct mtk_mmsys_routes *routes;
|
||||
const unsigned int num_routes;
|
||||
const u16 sw0_rst_offset;
|
||||
};
|
||||
|
||||
struct mtk_mmsys_match_data {
|
||||
unsigned short num_drv_data;
|
||||
const struct mtk_mmsys_driver_data *drv_data[];
|
||||
};
|
||||
|
||||
/*
|
||||
* Routes in mt8173, mt2701, mt2712 are different. That means
|
||||
* in the same register address, it controls different input/output
|
||||
|
|
|
@ -96,6 +96,20 @@
|
|||
#define MT8173_MUTEX_MOD_DISP_PWM1 24
|
||||
#define MT8173_MUTEX_MOD_DISP_OD 25
|
||||
|
||||
#define MT8195_MUTEX_MOD_DISP_OVL0 0
|
||||
#define MT8195_MUTEX_MOD_DISP_WDMA0 1
|
||||
#define MT8195_MUTEX_MOD_DISP_RDMA0 2
|
||||
#define MT8195_MUTEX_MOD_DISP_COLOR0 3
|
||||
#define MT8195_MUTEX_MOD_DISP_CCORR0 4
|
||||
#define MT8195_MUTEX_MOD_DISP_AAL0 5
|
||||
#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
|
||||
#define MT8195_MUTEX_MOD_DISP_DITHER0 7
|
||||
#define MT8195_MUTEX_MOD_DISP_DSI0 8
|
||||
#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
|
||||
#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
|
||||
#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
|
||||
#define MT8195_MUTEX_MOD_DISP_PWM0 27
|
||||
|
||||
#define MT2712_MUTEX_MOD_DISP_PWM2 10
|
||||
#define MT2712_MUTEX_MOD_DISP_OVL0 11
|
||||
#define MT2712_MUTEX_MOD_DISP_OVL1 12
|
||||
|
@ -132,9 +146,21 @@
|
|||
#define MT8167_MUTEX_SOF_DPI1 3
|
||||
#define MT8183_MUTEX_SOF_DSI0 1
|
||||
#define MT8183_MUTEX_SOF_DPI0 2
|
||||
#define MT8195_MUTEX_SOF_DSI0 1
|
||||
#define MT8195_MUTEX_SOF_DSI1 2
|
||||
#define MT8195_MUTEX_SOF_DP_INTF0 3
|
||||
#define MT8195_MUTEX_SOF_DP_INTF1 4
|
||||
#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
|
||||
#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
|
||||
|
||||
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
|
||||
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
|
||||
#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
|
||||
#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
|
||||
#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
|
||||
#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
|
||||
#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
|
||||
#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
|
||||
|
||||
struct mtk_mutex {
|
||||
int id;
|
||||
|
@ -149,6 +175,9 @@ enum mtk_mutex_sof_id {
|
|||
MUTEX_SOF_DPI1,
|
||||
MUTEX_SOF_DSI2,
|
||||
MUTEX_SOF_DSI3,
|
||||
MUTEX_SOF_DP_INTF0,
|
||||
MUTEX_SOF_DP_INTF1,
|
||||
DDP_MUTEX_SOF_MAX,
|
||||
};
|
||||
|
||||
struct mtk_mutex_data {
|
||||
|
@ -200,7 +229,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
|||
[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
|
||||
[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
|
||||
[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
|
||||
[DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
|
||||
[DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
|
||||
[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
|
||||
[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
|
||||
[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
|
||||
|
@ -233,7 +262,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
|||
[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
|
||||
[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
|
||||
[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
|
||||
[DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
|
||||
[DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
|
||||
[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
|
||||
[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
|
||||
[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
|
||||
|
@ -247,7 +276,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
|||
[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
|
||||
[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
|
||||
[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
|
||||
[DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
|
||||
[DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
|
||||
[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
|
||||
[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
|
||||
[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
|
||||
|
@ -260,7 +289,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
|||
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
|
||||
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
|
||||
[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
|
||||
[DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
|
||||
[DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
|
||||
[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
|
||||
[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
|
||||
[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
|
||||
|
@ -270,7 +299,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
|||
[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
|
||||
};
|
||||
|
||||
static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
|
||||
static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
|
||||
[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
|
||||
[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
|
||||
[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
|
||||
[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
|
||||
[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
|
||||
[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
|
||||
[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
|
||||
[DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
|
||||
[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
|
||||
[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
|
||||
[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
|
||||
[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
|
||||
[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
|
||||
};
|
||||
|
||||
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
|
||||
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
|
||||
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
|
||||
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
|
||||
|
@ -280,7 +325,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
|
|||
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
|
||||
};
|
||||
|
||||
static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
|
||||
static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
|
||||
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
|
||||
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
|
||||
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
|
||||
|
@ -288,7 +333,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
|
|||
};
|
||||
|
||||
/* Add EOF setting so overlay hardware can receive frame done irq */
|
||||
static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
|
||||
static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
|
||||
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
|
||||
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
|
||||
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
|
||||
|
@ -300,6 +345,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
|
|||
[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
|
||||
};
|
||||
|
||||
/*
|
||||
* To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
|
||||
* select the EOF source and configure the EOF plus timing from the
|
||||
* module that provides the timing signal.
|
||||
* So that MUTEX can not only send a STREAM_DONE event to GCE
|
||||
* but also detect the error at end of frame(EAEOF) when EOF signal
|
||||
* arrives.
|
||||
*/
|
||||
static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
|
||||
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
|
||||
[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
|
||||
[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
|
||||
[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
|
||||
[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
|
||||
[MUTEX_SOF_DP_INTF0] =
|
||||
MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
|
||||
[MUTEX_SOF_DP_INTF1] =
|
||||
MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
|
||||
};
|
||||
|
||||
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
|
||||
.mutex_mod = mt2701_mutex_mod,
|
||||
.mutex_sof = mt2712_mutex_sof,
|
||||
|
@ -351,6 +416,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
|
|||
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
|
||||
};
|
||||
|
||||
static const struct mtk_mutex_data mt8195_mutex_driver_data = {
|
||||
.mutex_mod = mt8195_mutex_mod,
|
||||
.mutex_sof = mt8195_mutex_sof,
|
||||
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
|
||||
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
|
||||
};
|
||||
|
||||
struct mtk_mutex *mtk_mutex_get(struct device *dev)
|
||||
{
|
||||
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
|
||||
|
@ -423,6 +495,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
|
|||
case DDP_COMPONENT_DPI1:
|
||||
sof_id = MUTEX_SOF_DPI1;
|
||||
break;
|
||||
case DDP_COMPONENT_DP_INTF0:
|
||||
sof_id = MUTEX_SOF_DP_INTF0;
|
||||
break;
|
||||
default:
|
||||
if (mtx->data->mutex_mod[id] < 32) {
|
||||
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
|
||||
|
@ -462,6 +537,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
|
|||
case DDP_COMPONENT_DSI3:
|
||||
case DDP_COMPONENT_DPI0:
|
||||
case DDP_COMPONENT_DPI1:
|
||||
case DDP_COMPONENT_DP_INTF0:
|
||||
writel_relaxed(MUTEX_SOF_SINGLE_MODE,
|
||||
mtx->regs +
|
||||
DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
|
||||
|
@ -587,6 +663,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
|
|||
.data = &mt8186_mutex_driver_data},
|
||||
{ .compatible = "mediatek,mt8192-disp-mutex",
|
||||
.data = &mt8192_mutex_driver_data},
|
||||
{ .compatible = "mediatek,mt8195-disp-mutex",
|
||||
.data = &mt8195_mutex_driver_data},
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
|
||||
|
|
|
@ -268,8 +268,6 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt);
|
|||
* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
|
||||
* packet and call back at the end of done packet
|
||||
* @pkt: the CMDQ packet
|
||||
* @cb: called at the end of done packet
|
||||
* @data: this data will pass back to cb
|
||||
*
|
||||
* Return: 0 for success; else the error code is returned
|
||||
*
|
||||
|
@ -277,7 +275,6 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt);
|
|||
* at the end of done packet. Note that this is an ASYNC function. When the
|
||||
* function returned, it may or may not be finished.
|
||||
*/
|
||||
int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
|
||||
void *data);
|
||||
int cmdq_pkt_flush_async(struct cmdq_pkt *pkt);
|
||||
|
||||
#endif /* __MTK_CMDQ_H__ */
|
||||
|
|
|
@ -17,13 +17,25 @@ enum mtk_ddp_comp_id {
|
|||
DDP_COMPONENT_COLOR0,
|
||||
DDP_COMPONENT_COLOR1,
|
||||
DDP_COMPONENT_DITHER,
|
||||
DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
|
||||
DDP_COMPONENT_DITHER1,
|
||||
DDP_COMPONENT_DP_INTF0,
|
||||
DDP_COMPONENT_DP_INTF1,
|
||||
DDP_COMPONENT_DPI0,
|
||||
DDP_COMPONENT_DPI1,
|
||||
DDP_COMPONENT_DSC0,
|
||||
DDP_COMPONENT_DSC1,
|
||||
DDP_COMPONENT_DSI0,
|
||||
DDP_COMPONENT_DSI1,
|
||||
DDP_COMPONENT_DSI2,
|
||||
DDP_COMPONENT_DSI3,
|
||||
DDP_COMPONENT_GAMMA,
|
||||
DDP_COMPONENT_MERGE0,
|
||||
DDP_COMPONENT_MERGE1,
|
||||
DDP_COMPONENT_MERGE2,
|
||||
DDP_COMPONENT_MERGE3,
|
||||
DDP_COMPONENT_MERGE4,
|
||||
DDP_COMPONENT_MERGE5,
|
||||
DDP_COMPONENT_OD0,
|
||||
DDP_COMPONENT_OD1,
|
||||
DDP_COMPONENT_OVL0,
|
||||
|
|
Loading…
Reference in New Issue