ARM: S3C24XX: transform s3c2440 irqs into new structure
As always a mapping structure is everything needed. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Heiko Stuebner
Kukjin Kim
parent
70644ade48
commit
f0301673ff
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@ -729,150 +729,78 @@ void __init s3c2416_init_irq(void)
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#endif
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#ifdef CONFIG_CPU_S3C244X
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/* camera irq */
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static void s3c_irq_demux_cam(unsigned int irq,
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struct irq_desc *desc)
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{
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unsigned int subsrc, submsk;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= 11;
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subsrc &= 3;
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if (subsrc != 0) {
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if (subsrc & 1) {
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generic_handle_irq(IRQ_S3C2440_CAM_C);
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}
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if (subsrc & 2) {
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generic_handle_irq(IRQ_S3C2440_CAM_P);
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}
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}
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}
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#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
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static void
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s3c_irq_cam_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
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}
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static void
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s3c_irq_cam_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_CAM);
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}
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static void
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s3c_irq_cam_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
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}
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static struct irq_chip s3c_irq_cam = {
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.irq_mask = s3c_irq_cam_mask,
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.irq_unmask = s3c_irq_cam_unmask,
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.irq_ack = s3c_irq_cam_ack,
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#ifdef CONFIG_CPU_S3C2440
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static struct s3c_irq_data init_s3c2440base[32] = {
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{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
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{ .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
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{ .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
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{ .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
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{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
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{ .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
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{ .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
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{ .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
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{ .type = S3C_IRQTYPE_EDGE, }, /* TICK */
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{ .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
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{ .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* LCD */
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{ .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* SDI */
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{ .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
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{ .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
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{ .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
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{ .type = S3C_IRQTYPE_EDGE, }, /* USBD */
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{ .type = S3C_IRQTYPE_EDGE, }, /* USBH */
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{ .type = S3C_IRQTYPE_EDGE, }, /* IIC */
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{ .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
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{ .type = S3C_IRQTYPE_EDGE, }, /* RTC */
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{ .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
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};
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#ifdef CONFIG_CPU_S3C2440
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/* WDT/AC97 */
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static void s3c_irq_demux_wdtac97(unsigned int irq,
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struct irq_desc *desc)
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{
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unsigned int subsrc, submsk;
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/* read the current pending interrupts, and the mask
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* for what it is available */
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subsrc = __raw_readl(S3C2410_SUBSRCPND);
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submsk = __raw_readl(S3C2410_INTSUBMSK);
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subsrc &= ~submsk;
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subsrc >>= 13;
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subsrc &= 3;
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if (subsrc != 0) {
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if (subsrc & 1) {
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generic_handle_irq(IRQ_S3C2440_WDT);
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}
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if (subsrc & 2) {
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generic_handle_irq(IRQ_S3C2440_AC97);
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}
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}
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}
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#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
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static void
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s3c_irq_wdtac97_mask(struct irq_data *data)
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{
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s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
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}
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static void
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s3c_irq_wdtac97_unmask(struct irq_data *data)
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{
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s3c_irqsub_unmask(data->irq, INTMSK_WDT);
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}
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static void
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s3c_irq_wdtac97_ack(struct irq_data *data)
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{
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s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
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}
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static struct irq_chip s3c_irq_wdtac97 = {
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.irq_mask = s3c_irq_wdtac97_mask,
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.irq_unmask = s3c_irq_wdtac97_unmask,
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.irq_ack = s3c_irq_wdtac97_ack,
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static struct s3c_irq_data init_s3c2440subint[32] = {
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
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{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
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{ .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* TC */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* ADC */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
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{ .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
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};
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void __init s3c2440_init_irq(void)
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{
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unsigned int irqno;
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struct s3c_irq_intc *main_intc;
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printk("S3C2440: IRQ Support\n");
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pr_info("S3C2440: IRQ Support\n");
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s3c24xx_init_irq();
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#ifdef CONFIG_FIQ
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init_FIQ(FIQ_START);
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#endif
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irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
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handle_level_irq);
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set_irq_flags(IRQ_NFCON, IRQF_VALID);
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/* add chained handler for camera */
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irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
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handle_level_irq);
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irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
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for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
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irq_set_chip_and_handler(irqno, &s3c_irq_cam,
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handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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main_intc = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL, 0x4a000000);
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if (IS_ERR(main_intc)) {
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pr_err("irq: could not create main interrupt controller\n");
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return;
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}
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/* add new chained handler for wdt, ac7 */
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irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
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handle_level_irq);
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irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
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for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
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irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
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handle_level_irq);
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set_irq_flags(irqno, IRQF_VALID);
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}
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s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
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s3c24xx_init_intc(NULL, &init_s3c2440subint[0], main_intc, 0x4a000018);
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}
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#endif
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@ -949,8 +877,6 @@ void __init s3c2442_init_irq(void)
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}
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#endif
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#endif
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#ifdef CONFIG_CPU_S3C2443
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static struct s3c_irq_data init_s3c2443base[32] = {
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{ .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
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