ASoC: topology: use inclusive language for bclk and fsync

Mirror suggested changes in alsa-lib.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20201112163100.5081-2-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Pierre-Louis Bossart 2020-11-12 10:30:57 -06:00 committed by Mark Brown
parent a5a8ac3ca0
commit f026c12300
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GPG Key ID: 24D68B725D5487D0
4 changed files with 48 additions and 34 deletions

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@ -72,21 +72,29 @@ struct snd_compr_stream;
#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */
/*
* DAI hardware clock masters.
* DAI hardware clock providers/consumers
*
* This is wrt the codec, the inverse is true for the interface
* i.e. if the codec is clk and FRM master then the interface is
* clk and frame secondary.
* i.e. if the codec is clk and FRM provider then the interface is
* clk and frame consumer.
*/
#define SND_SOC_DAIFMT_CBM_CFM (1 << 12) /* codec clk & FRM master */
#define SND_SOC_DAIFMT_CBS_CFM (2 << 12) /* codec clk secondary & FRM master */
#define SND_SOC_DAIFMT_CBM_CFS (3 << 12) /* codec clk master & frame secondary */
#define SND_SOC_DAIFMT_CBS_CFS (4 << 12) /* codec clk & FRM secondary */
#define SND_SOC_DAIFMT_CBP_CFP (1 << 12) /* codec clk provider & frame provider */
#define SND_SOC_DAIFMT_CBC_CFP (2 << 12) /* codec clk consumer & frame provider */
#define SND_SOC_DAIFMT_CBP_CFC (3 << 12) /* codec clk provider & frame consumer */
#define SND_SOC_DAIFMT_CBC_CFC (4 << 12) /* codec clk consumer & frame follower */
#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f
#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0
#define SND_SOC_DAIFMT_INV_MASK 0x0f00
#define SND_SOC_DAIFMT_MASTER_MASK 0xf000
/* previous definitions kept for backwards-compatibility, do not use in new contributions */
#define SND_SOC_DAIFMT_CBM_CFM SND_SOC_DAIFMT_CBP_CFP
#define SND_SOC_DAIFMT_CBS_CFM SND_SOC_DAIFMT_CBC_CFP
#define SND_SOC_DAIFMT_CBM_CFS SND_SOC_DAIFMT_CBP_CFC
#define SND_SOC_DAIFMT_CBS_CFS SND_SOC_DAIFMT_CBC_CFC
#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f
#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0
#define SND_SOC_DAIFMT_INV_MASK 0x0f00
#define SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK 0xf000
#define SND_SOC_DAIFMT_MASTER_MASK SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK
/*
* Master Clock Directions

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@ -170,16 +170,22 @@
#define SND_SOC_TPLG_LNK_FLGBIT_VOICE_WAKEUP (1 << 3)
/* DAI topology BCLK parameter
* For the backwards capability, by default codec is bclk master
* For the backwards capability, by default codec is bclk provider
*/
#define SND_SOC_TPLG_BCLK_CM 0 /* codec is bclk master */
#define SND_SOC_TPLG_BCLK_CS 1 /* codec is bclk slave */
#define SND_SOC_TPLG_BCLK_CP 0 /* codec is bclk provider */
#define SND_SOC_TPLG_BCLK_CC 1 /* codec is bclk consumer */
/* keep previous definitions for compatibility */
#define SND_SOC_TPLG_BCLK_CM SND_SOC_TPLG_BCLK_CP
#define SND_SOC_TPLG_BCLK_CS SND_SOC_TPLG_BCLK_CC
/* DAI topology FSYNC parameter
* For the backwards capability, by default codec is fsync master
* For the backwards capability, by default codec is fsync provider
*/
#define SND_SOC_TPLG_FSYNC_CM 0 /* codec is fsync master */
#define SND_SOC_TPLG_FSYNC_CS 1 /* codec is fsync slave */
#define SND_SOC_TPLG_FSYNC_CP 0 /* codec is fsync provider */
#define SND_SOC_TPLG_FSYNC_CC 1 /* codec is fsync consumer */
/* keep previous definitions for compatibility */
#define SND_SOC_TPLG_FSYNC_CM SND_SOC_TPLG_FSYNC_CP
#define SND_SOC_TPLG_FSYNC_CS SND_SOC_TPLG_FSYNC_CC
/*
* Block Header.
@ -336,8 +342,8 @@ struct snd_soc_tplg_hw_config {
__u8 clock_gated; /* SND_SOC_TPLG_DAI_CLK_GATE_ value */
__u8 invert_bclk; /* 1 for inverted BCLK, 0 for normal */
__u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */
__u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */
__u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */
__u8 bclk_provider; /* SND_SOC_TPLG_BCLK_ value */
__u8 fsync_provider; /* SND_SOC_TPLG_FSYNC_ value */
__u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */
__le16 reserved; /* for 32bit alignment */
__le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */

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@ -2017,7 +2017,7 @@ static void set_link_hw_format(struct snd_soc_dai_link *link,
struct snd_soc_tplg_link_config *cfg)
{
struct snd_soc_tplg_hw_config *hw_config;
unsigned char bclk_master, fsync_master;
unsigned char bclk_provider, fsync_provider;
unsigned char invert_bclk, invert_fsync;
int i;
@ -2057,18 +2057,18 @@ static void set_link_hw_format(struct snd_soc_dai_link *link,
link->dai_fmt |= SND_SOC_DAIFMT_IB_IF;
/* clock masters */
bclk_master = (hw_config->bclk_master ==
SND_SOC_TPLG_BCLK_CM);
fsync_master = (hw_config->fsync_master ==
SND_SOC_TPLG_FSYNC_CM);
if (bclk_master && fsync_master)
link->dai_fmt |= SND_SOC_DAIFMT_CBM_CFM;
else if (!bclk_master && fsync_master)
link->dai_fmt |= SND_SOC_DAIFMT_CBS_CFM;
else if (bclk_master && !fsync_master)
link->dai_fmt |= SND_SOC_DAIFMT_CBM_CFS;
bclk_provider = (hw_config->bclk_provider ==
SND_SOC_TPLG_BCLK_CP);
fsync_provider = (hw_config->fsync_provider ==
SND_SOC_TPLG_FSYNC_CP);
if (bclk_provider && fsync_provider)
link->dai_fmt |= SND_SOC_DAIFMT_CBP_CFP;
else if (!bclk_provider && fsync_provider)
link->dai_fmt |= SND_SOC_DAIFMT_CBC_CFP;
else if (bclk_provider && !fsync_provider)
link->dai_fmt |= SND_SOC_DAIFMT_CBP_CFC;
else
link->dai_fmt |= SND_SOC_DAIFMT_CBS_CFS;
link->dai_fmt |= SND_SOC_DAIFMT_CBC_CFC;
}
}

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@ -2777,15 +2777,15 @@ static void sof_dai_set_format(struct snd_soc_tplg_hw_config *hw_config,
struct sof_ipc_dai_config *config)
{
/* clock directions wrt codec */
if (hw_config->bclk_master == SND_SOC_TPLG_BCLK_CM) {
if (hw_config->bclk_provider == SND_SOC_TPLG_BCLK_CM) {
/* codec is bclk master */
if (hw_config->fsync_master == SND_SOC_TPLG_FSYNC_CM)
if (hw_config->fsync_provider == SND_SOC_TPLG_FSYNC_CM)
config->format |= SOF_DAI_FMT_CBM_CFM;
else
config->format |= SOF_DAI_FMT_CBM_CFS;
} else {
/* codec is bclk slave */
if (hw_config->fsync_master == SND_SOC_TPLG_FSYNC_CM)
if (hw_config->fsync_provider == SND_SOC_TPLG_FSYNC_CM)
config->format |= SOF_DAI_FMT_CBS_CFM;
else
config->format |= SOF_DAI_FMT_CBS_CFS;