sh: mach-sdk7786: FPGA updates.
This does a bit of refactoring of the FPGA management code. The primary FPGA initialization is moved out to its own file in preparation for implementing some of the more complex capabilities, a complete set of register definitions is provided, and all of the existing users in the board code are moved over to use the new interface instead of setting up overlapping mappings. This also corrects the FPGA size, which previously was chomped off at the SDIF control register. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
bdc27300f5
commit
efd590d57a
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@ -1 +1 @@
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obj-y := setup.o
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obj-y := setup.o fpga.o
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@ -0,0 +1,37 @@
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/*
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* SDK7786 FPGA Support.
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*
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* Copyright (C) 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/bcd.h>
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#include <mach/fpga.h>
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#define FPGA_REGS_BASE 0x07fff800
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#define FPGA_REGS_SIZE 0x490
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void __iomem *sdk7786_fpga_base;
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void __init sdk7786_fpga_init(void)
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{
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u16 version, date;
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sdk7786_fpga_base = ioremap_nocache(FPGA_REGS_BASE, FPGA_REGS_SIZE);
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if (unlikely(!sdk7786_fpga_base)) {
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panic("FPGA remapping failed.\n");
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return;
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}
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version = fpga_read_reg(FPGAVR);
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date = fpga_read_reg(FPGADR);
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pr_info("\tFPGA version:\t%d.%d (built on %d/%d/%d)\n",
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bcd2bin(version >> 8) & 0xf, bcd2bin(version & 0xf),
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((date >> 12) & 0xf) + 2000,
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(date >> 8) & 0xf, bcd2bin(date & 0xff));
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}
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@ -18,6 +18,7 @@
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#include <asm/machvec.h>
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#include <asm/heartbeat.h>
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#include <asm/sizes.h>
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#include <mach/fpga.h>
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static struct resource heartbeat_resource = {
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.start = 0x07fff8b0,
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@ -103,27 +104,17 @@ static struct platform_device *sh7786_devices[] __initdata = {
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&smbus_pcie_device,
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};
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#define SBCR_REGS_BASE 0x07fff990
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#define SCBR_I2CMEN (1 << 0) /* FPGA I2C master enable */
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#define SCBR_I2CCEN (1 << 1) /* CPU I2C master enable */
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static int sdk7786_i2c_setup(void)
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{
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void __iomem *sbcr;
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unsigned int tmp;
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sbcr = ioremap_nocache(SBCR_REGS_BASE, SZ_16);
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/*
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* Hand over I2C control to the FPGA.
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*/
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tmp = ioread16(sbcr);
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tmp = fpga_read_reg(SBCR);
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tmp &= ~SCBR_I2CCEN;
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tmp |= SCBR_I2CMEN;
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iowrite16(tmp, sbcr);
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iounmap(sbcr);
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fpga_write_reg(tmp, SBCR);
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return i2c_register_board_info(0, sdk7786_i2c_devices,
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ARRAY_SIZE(sdk7786_i2c_devices));
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@ -141,43 +132,6 @@ static int __init sdk7786_devices_setup(void)
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}
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__initcall(sdk7786_devices_setup);
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#define FPGA_REGS_BASE 0x07fff800
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#define FPGA_REGS_SIZE 1152
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#define INTASR 0x010
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#define INTAMR 0x020
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#define INTBSR 0x090
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#define INTBMR 0x0a0
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#define INTMSR 0x130
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#define IASELR1 0x210
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#define IASELR2 0x220
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#define IASELR3 0x230
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#define IASELR4 0x240
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#define IASELR5 0x250
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#define IASELR6 0x260
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#define IASELR7 0x270
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#define IASELR8 0x280
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#define IASELR9 0x290
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#define IASELR10 0x2a0
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#define IASELR11 0x2b0
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#define IASELR12 0x2c0
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#define IASELR13 0x2d0
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#define IASELR14 0x2e0
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#define IASELR15 0x2f0
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static void __iomem *fpga_regs;
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static u16 fpga_read_reg(unsigned int reg)
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{
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return __raw_readw(fpga_regs + reg);
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}
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static void fpga_write_reg(u16 val, unsigned int reg)
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{
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__raw_writew(val, fpga_regs + reg);
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}
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enum {
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ATA_IRQ_BIT = 1,
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SPI_BUSY_BIT = 2,
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@ -197,12 +151,6 @@ static void __init init_sdk7786_IRQ(void)
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{
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unsigned int tmp;
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fpga_regs = ioremap_nocache(FPGA_REGS_BASE, FPGA_REGS_SIZE);
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if (!fpga_regs) {
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printk(KERN_ERR "Couldn't map FPGA registers\n");
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return;
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}
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/* Enable priority encoding for all IRLs */
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fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
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@ -219,21 +167,9 @@ static void __init init_sdk7786_IRQ(void)
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plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
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}
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#define MODSWR_REGS 0x07fff830
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static int sdk7786_mode_pins(void)
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{
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void __iomem *modswr;
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int pin_states;
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modswr = ioremap_nocache(MODSWR_REGS, SZ_16);
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if (!modswr)
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return -ENXIO;
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pin_states = ioread16(modswr);
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iounmap(modswr);
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return pin_states;
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return fpga_read_reg(MODSWR);
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}
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static int sdk7786_clk_init(void)
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@ -260,7 +196,11 @@ static int sdk7786_clk_init(void)
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/* Initialize the board */
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static void __init sdk7786_setup(char **cmdline_p)
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{
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printk(KERN_INFO "Renesas Technology Corp. SDK7786 support.\n");
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pr_info("Renesas Technology Europe SDK7786 support:\n");
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sdk7786_fpga_init();
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pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
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}
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/*
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@ -0,0 +1,112 @@
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#ifndef __MACH_SDK7786_FPGA_H
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#define __MACH_SDK7786_FPGA_H
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#define SRSTR 0x000
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#define INTASR 0x010
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#define INTAMR 0x020
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#define MODSWR 0x030
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#define INTTESTR 0x040
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#define SYSSR 0x050
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#define NRGPR 0x060
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#define NMISR 0x070
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#define NMIMR 0x080
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#define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */
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#define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */
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#define INTBSR 0x090
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#define INTBMR 0x0a0
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#define USRLEDR 0x0b0
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#define MAPSWR 0x0c0
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#define FPGAVR 0x0d0
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#define FPGADR 0x0e0
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#define PCBRR 0x0f0
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#define RSR 0x100
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#define EXTASR 0x110
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#define SPCAR 0x120
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#define INTMSR 0x130
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#define PCIECR 0x140
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#define FAER 0x150
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#define USRGPIR 0x160
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/* 0x170 reserved */
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#define LCLASR 0x180
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#define SBCR 0x190
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#define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */
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#define SCBR_I2CCEN BIT(1) /* CPU I2C master enable */
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#define PWRCR 0x1a0
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#define SPCBR 0x1b0
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#define SPICR 0x1c0
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#define SPIDR 0x1d0
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#define I2CCR 0x1e0
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#define I2CDR 0x1f0
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#define FPGACR 0x200
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#define IASELR1 0x210
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#define IASELR2 0x220
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#define IASELR3 0x230
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#define IASELR4 0x240
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#define IASELR5 0x250
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#define IASELR6 0x260
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#define IASELR7 0x270
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#define IASELR8 0x280
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#define IASELR9 0x290
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#define IASELR10 0x2a0
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#define IASELR11 0x2b0
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#define IASELR12 0x2c0
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#define IASELR13 0x2d0
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#define IASELR14 0x2e0
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#define IASELR15 0x2f0
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/* 0x300 reserved */
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#define IBSELR1 0x310
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#define IBSELR2 0x320
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#define IBSELR3 0x330
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#define IBSELR4 0x340
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#define IBSELR5 0x350
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#define IBSELR6 0x360
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#define IBSELR7 0x370
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#define IBSELR8 0x380
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#define IBSELR9 0x390
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#define IBSELR10 0x3a0
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#define IBSELR11 0x3b0
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#define IBSELR12 0x3c0
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#define IBSELR13 0x3d0
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#define IBSELR14 0x3e0
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#define IBSELR15 0x3f0
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#define USRACR 0x400
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#define BEEPR 0x410
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#define USRLCDR 0x420
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#define SMBCR 0x430
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#define SMBDR 0x440
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#define USBCR 0x450
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#define AMSR 0x460
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#define ACCR 0x470
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#define SDIFCR 0x480
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/* arch/sh/boards/mach-sdk7786/fpga.c */
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extern void __iomem *sdk7786_fpga_base;
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extern void sdk7786_fpga_init(void);
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#define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg))
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/*
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* A convenience wrapper from register offset to internal I2C address,
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* when the FPGA is in I2C slave mode.
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*/
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#define SDK7786_FPGA_I2CADDR(reg) ((reg) >> 3)
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static inline u16 fpga_read_reg(unsigned int reg)
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{
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return ioread16(sdk7786_fpga_base + reg);
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}
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static inline void fpga_write_reg(u16 val, unsigned int reg)
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{
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iowrite16(val, sdk7786_fpga_base + reg);
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}
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#endif /* __MACH_SDK7786_FPGA_H */
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