drm/i915/skl: Adjust the port PLL selection code
Skylake deprecates the usage of PORT_CLK_SEL and we are advised to use the new DPLL_CRTL2 for the DDI->PLL mapping. v2: Modified as per review comments Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -1243,7 +1243,8 @@ void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
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static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
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{
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struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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int type = intel_encoder->type;
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@ -1253,8 +1254,22 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
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intel_edp_panel_on(intel_dp);
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}
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WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
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I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
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if (IS_SKYLAKE(dev)) {
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uint32_t dpll = crtc->config.ddi_pll_sel;
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uint32_t val;
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val = I915_READ(DPLL_CTRL2);
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val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
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DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
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val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
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DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
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I915_WRITE(DPLL_CTRL2, val);
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} else {
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WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE);
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I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel);
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}
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if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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@ -1278,7 +1293,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
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static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
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{
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struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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struct drm_device *dev = encoder->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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int type = intel_encoder->type;
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uint32_t val;
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@ -1306,7 +1322,11 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
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intel_edp_panel_off(intel_dp);
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}
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I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
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if (IS_SKYLAKE(dev))
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I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
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DPLL_CTRL2_DDI_CLK_OFF(port)));
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else
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I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
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}
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static void intel_enable_ddi(struct intel_encoder *intel_encoder)
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