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cacheinfo: Add use_arch[|_cache]_info field/function 

The cache information can be extracted from either a Device
Tree (DT), the PPTT ACPI table, or arch registers (clidr_el1
for arm64).

The clidr_el1 register is used only if DT/ACPI information is not
available. It does not states how caches are shared among CPUs.

Add a use_arch_cache_info field/function to identify when the
DT/ACPI doesn't provide cache information. Use this information
to assume L1 caches are privates and L2 and higher are shared among
all CPUs.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20230414081453.244787-5-pierre.gondois@arm.com
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
This commit is contained in:
Pierre Gondois 2023-04-14 10:14:52 +02:00 committed by Sudeep Holla
parent 3522340199
commit ef9f643a9f
2 changed files with 16 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/base/cacheinfo.c
View File

@ -28,6 +28,9 @@ static DEFINE_PER_CPU(struct cpu_cacheinfo, ci_cpu_cacheinfo);
#define per_cpu_cacheinfo_idx(cpu, idx) \ #define per_cpu_cacheinfo_idx(cpu, idx) \
(per_cpu_cacheinfo(cpu) + (idx)) (per_cpu_cacheinfo(cpu) + (idx))
/* Set if no cache information is found in DT/ACPI. */
static bool use_arch_info;
struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu) struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu)
{ {
return ci_cacheinfo(cpu); return ci_cacheinfo(cpu);
@ -40,7 +43,8 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf,
* For non DT/ACPI systems, assume unique level 1 caches, * For non DT/ACPI systems, assume unique level 1 caches,
* system-wide shared caches for all other levels. * system-wide shared caches for all other levels.
*/ */
if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI))) if (!(IS_ENABLED(CONFIG_OF) || IS_ENABLED(CONFIG_ACPI)) ||
use_arch_info)
return (this_leaf->level != 1) && (sib_leaf->level != 1); return (this_leaf->level != 1) && (sib_leaf->level != 1);
if ((sib_leaf->attributes & CACHE_ID) && if ((sib_leaf->attributes & CACHE_ID) &&
@ -343,6 +347,10 @@ static int cache_setup_properties(unsigned int cpu)
else if (!acpi_disabled) else if (!acpi_disabled)
ret = cache_setup_acpi(cpu); ret = cache_setup_acpi(cpu);
// Assume there is no cache information available in DT/ACPI from now.
if (ret && use_arch_cache_info())
use_arch_info = true;
return ret; return ret;
} }
@ -361,7 +369,7 @@ static int cache_shared_cpu_map_setup(unsigned int cpu)
* to update the shared cpu_map if the cache attributes were * to update the shared cpu_map if the cache attributes were
* populated early before all the cpus are brought online * populated early before all the cpus are brought online
*/ */
if (!last_level_cache_is_valid(cpu)) { if (!last_level_cache_is_valid(cpu) && !use_arch_info) {
ret = cache_setup_properties(cpu); ret = cache_setup_properties(cpu);
if (ret) if (ret)
return ret; return ret;

6
include/linux/cacheinfo.h
View File

@ -131,4 +131,10 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level)
return -1; return -1;
} }
#ifdef CONFIG_ARM64
#define use_arch_cache_info() (true)
#else
#define use_arch_cache_info() (false)
#endif
#endif /* _LINUX_CACHEINFO_H */ #endif /* _LINUX_CACHEINFO_H */