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drm/i915: make update_wm take a dev_priv. 

The crtc was never being used here.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/70438bface47fa683cda8a9e95d0556fca448172.1632869550.git.jani.nikula@intel.com
This commit is contained in:
Dave Airlie 2021-09-29 01:57:47 +03:00 committed by Jani Nikula
parent 758b2fc266
commit ef9c66a0ae
4 changed files with 14 additions and 20 deletions
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10
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -2383,7 +2383,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
intel_update_watermarks(crtc);
intel_update_watermarks(dev_priv);
if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
hsw_enable_ips(new_crtc_state);
@ -2540,7 +2540,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else if (new_crtc_state->update_wm_pre)
intel_update_watermarks(crtc);
intel_update_watermarks(dev_priv);
}
/*
@ -3587,7 +3587,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else
intel_update_watermarks(crtc);
intel_update_watermarks(dev_priv);
intel_enable_transcoder(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@ -3654,7 +3654,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
intel_update_watermarks(crtc);
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
@ -3730,7 +3730,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
encoder->base.crtc = NULL;
intel_fbc_disable(crtc);
intel_update_watermarks(crtc);
intel_update_watermarks(dev_priv);
intel_disable_shared_dpll(crtc_state);
intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);

2
drivers/gpu/drm/i915/i915_drv.h
View File

@ -341,7 +341,7 @@ struct drm_i915_display_funcs {
void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
void (*update_wm)(struct intel_crtc *crtc);
void (*update_wm)(struct drm_i915_private *dev_priv);
int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
/* Returns the active state of the crtc, and if the crtc is active,

20
drivers/gpu/drm/i915/intel_pm.c
View File

@ -881,9 +881,8 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
return enabled;
}
static void pnv_update_wm(struct intel_crtc *unused_crtc)
static void pnv_update_wm(struct drm_i915_private *dev_priv)
{
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct cxsr_latency *latency;
u32 reg;
@ -2248,9 +2247,8 @@ static void vlv_optimize_watermarks(struct intel_atomic_state *state,
mutex_unlock(&dev_priv->wm.wm_mutex);
}
static void i965_update_wm(struct intel_crtc *unused_crtc)
static void i965_update_wm(struct drm_i915_private *dev_priv)
{
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
@ -2324,9 +2322,8 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
#undef FW_WM
static void i9xx_update_wm(struct intel_crtc *unused_crtc)
static void i9xx_update_wm(struct drm_i915_private *dev_priv)
{
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
const struct intel_watermark_params *wm_info;
u32 fwater_lo;
u32 fwater_hi;
@ -2476,9 +2473,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
intel_set_memory_cxsr(dev_priv, true);
}
static void i845_update_wm(struct intel_crtc *unused_crtc)
static void i845_update_wm(struct drm_i915_private *dev_priv)
{
struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct drm_display_mode *pipe_mode;
u32 fwater_lo;
@ -7136,7 +7132,7 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
/**
* intel_update_watermarks - update FIFO watermark values based on current modes
* @crtc: the #intel_crtc on which to compute the WM
* @dev_priv: i915 device
*
* Calculate watermark values for the various WM regs based on current mode
* and plane configuration.
@ -7167,12 +7163,10 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
* We don't use the sprite, so we can ignore that. And on Crestline we have
* to set the non-SR watermarks to 8.
*/
void intel_update_watermarks(struct intel_crtc *crtc)
void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
if (dev_priv->display.update_wm)
dev_priv->display.update_wm(crtc);
dev_priv->display.update_wm(dev_priv);
}
void intel_enable_ipc(struct drm_i915_private *dev_priv)

2
drivers/gpu/drm/i915/intel_pm.h
View File

@ -29,7 +29,7 @@ struct skl_wm_level;
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
void intel_suspend_hw(struct drm_i915_private *dev_priv);
int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
void intel_update_watermarks(struct intel_crtc *crtc);
void intel_update_watermarks(struct drm_i915_private *dev_priv);
void intel_init_pm(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
void intel_pm_setup(struct drm_i915_private *dev_priv);