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crypto: caam - Add definition of rd/wr_reg64 for little endian platform 

CAAM IP has certain 64 bit registers . 32 bit architectures cannot force
atomic-64 operations.  This patch adds definition of these atomic-64
operations for little endian platforms. The definitions which existed
previously were for big endian platforms.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Ruchika Gupta 2014-06-23 18:49:30 +05:30 committed by Herbert Xu
parent 17157c90a8
commit ef94b1d834
1 changed files with 16 additions and 0 deletions
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16
drivers/crypto/caam/regs.h
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@ -84,6 +84,7 @@
#endif #endif
#ifndef CONFIG_64BIT #ifndef CONFIG_64BIT
#ifdef __BIG_ENDIAN
static inline void wr_reg64(u64 __iomem *reg, u64 data) static inline void wr_reg64(u64 __iomem *reg, u64 data)
{ {
wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32); wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32);
@ -95,6 +96,21 @@ static inline u64 rd_reg64(u64 __iomem *reg)
return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) | return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) |
((u64)rd_reg32((u32 __iomem *)reg + 1)); ((u64)rd_reg32((u32 __iomem *)reg + 1));
} }
#else
#ifdef __LITTLE_ENDIAN
static inline void wr_reg64(u64 __iomem *reg, u64 data)
{
wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32);
wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull);
}
static inline u64 rd_reg64(u64 __iomem *reg)
{
return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) |
((u64)rd_reg32((u32 __iomem *)reg));
}
#endif
#endif
#endif #endif
/* /*