usb: dwc2: gadget: Start DDMA IN status phase in StsPhseRcvd handler
In DDMA mode of operation IN status phase of control write transfer should start after getting StsPhseRcvd interrupt. This interrupt is issued by HW once host starts to send IN tokens after data stage. Signed-off-by: Vahram Aharonyan <vahrama@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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@ -1991,7 +1991,9 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
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*/
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*/
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}
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}
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if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
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/* DDMA IN status phase will start from StsPhseRcvd interrupt */
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if (!using_desc_dma(hsotg) && epnum == 0 &&
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hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
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/* Move to STATUS IN */
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/* Move to STATUS IN */
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dwc2_hsotg_ep0_zlp(hsotg, true);
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dwc2_hsotg_ep0_zlp(hsotg, true);
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return;
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return;
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@ -2614,9 +2616,14 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
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}
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}
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}
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}
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if (ints & DXEPINT_STSPHSERCVD)
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if (ints & DXEPINT_STSPHSERCVD) {
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dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
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dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
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/* Move to STATUS IN for DDMA */
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if (using_desc_dma(hsotg))
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dwc2_hsotg_ep0_zlp(hsotg, true);
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}
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if (ints & DXEPINT_BACK2BACKSETUP)
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if (ints & DXEPINT_BACK2BACKSETUP)
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dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
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dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
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