Qualcomm ARM64 Updates for v4.10
* Add Hexagon SMD/PIL nodes * Add DB820c PMIC pins * Fixup APQ8016 voltage ranges * Add various MSM8996 nodes to support SMD/SMEM/SMP2P * Add support for Huawei Nexus 6P (Angler) * Add support for LG Nexus 5x (Bullhead) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYJ/UbAAoJEFKiBbHx2RXVdeEP/jucpOousGzXUgHYAwwJLqDx RmBQu+lMmYHv7N3euCyIgJ74ZorMbVANO/NKoLpWFuaoFEZfBXckytulkTkNt3Qi 2HvfxUYVthm0Gwucrc6xe0Pr9XVdNJQbIvfREvt2QM2H2SzO5nrIL/M2JDzjTFAR OYh7OqvpR6LSl9SfLi02caoA08180R4jHpWJXuKYUZSMy6JGVsdyVqkLvoKS+xgo C6ANTXjYVsHY5iFYACBipusucHkOM4qAw9pkvJd2AI2XdT/lNhnXkBAtNkvDsVek euJ8EmyIeSZo+mnMzDvOt10nSSvTppJZ31AJMEG5WB/uRZsCj1rtK0coV3k3ejTf elDeHvu5IWRxPfMQ+pEgRNZhgGvIieUPiRfspAZJ2xkHgroDkwrNXrP43Z1PJY9H qFEHmjE05ScXcnyNEeEVwK6PYRM1uey7gNgHgkU09xZmj/9GVnnYURuLbKYx3oKV lG0kaJNgU0THirtAlYjbc0Y4T1Y9juaOAThwt+P4x9kXFf0BGvqMnbxyyp/ecrTN 94K8Te8tnl0m5iPZ1DgwZwPaL2M5Xc6ROwcnQslvcdQbjU5XKsr3ZELNdxmWApqi HvFucNJP1fGt/pmeLfR1oMMSIvy2dybTjq0tB3krgTKusxoyWsem2WXLWd8xjUTo 0vhukntWZ17Q7c10Ye1r =85aH -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64 Qualcomm ARM64 Updates for v4.10 * Add Hexagon SMD/PIL nodes * Add DB820c PMIC pins * Fixup APQ8016 voltage ranges * Add various MSM8996 nodes to support SMD/SMEM/SMP2P * Add support for Huawei Nexus 6P (Angler) * Add support for LG Nexus 5x (Bullhead) * tag 'qcom-arm64-for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support dt-bindings: qcom: Add msm899(2/4) bindings arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support arm64: dts: msm8996: Add SMP2P and APCS nodes arm64: dts: msm8996: Add SMEM DT nodes arm64: dts: msm8996: Add reserve-memory nodes arm64: dts: msm8996: Add SMEM reserve-memory node arm64: dts: apq8016-sbc: add analog audio support with multicodec arm64: dts: qcom: Add missing interrupt entry for pm8994 gpios arm64: dts: apq8016-sbc: Set up LDO2, LDO6 and LDO17 regulator voltage ranges dts: arm64: db820c: add pmic pins specific dts file arm64: dts: qcom: msm8916: Add Hexagon PIL node arm64: dts: qcom: msm8916: Add Hexagon SMD edge Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
eed67c9951
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@ -21,6 +21,8 @@ The 'SoC' element must be one of the following strings:
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apq8096
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msm8916
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msm8974
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msm8992
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msm8994
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msm8996
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The 'board' element must be one of the following strings:
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@ -1,6 +1,9 @@
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dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
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dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
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dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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@ -15,6 +15,7 @@
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#include "pm8916.dtsi"
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#include "apq8016-sbc-soc-pins.dtsi"
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#include "apq8016-sbc-pmic-pins.dtsi"
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#include <dt-bindings/sound/apq8016-lpass.h>
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/ {
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aliases {
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@ -251,6 +252,60 @@
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vddio-supply = <&pm8916_l6>;
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};
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};
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lpass_codec: codec{
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status = "okay";
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};
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/*
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Internal Codec
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playback - Primary MI2S
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capture - Ter MI2S
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External Primary:
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playback - secondary MI2S
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capture - Quat MI2S
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External Secondary:
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playback - Quat MI2S
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capture - Quat MI2S
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*/
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sound: sound {
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compatible = "qcom,apq8016-sbc-sndcard";
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reg = <0x07702000 0x4>, <0x07702004 0x4>;
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reg-names = "mic-iomux", "spkr-iomux";
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status = "okay";
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pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
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pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
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pinctrl-names = "default", "sleep";
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qcom,model = "DB410c";
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qcom,audio-routing =
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"AMIC2", "MIC BIAS Internal2",
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"AMIC3", "MIC BIAS External1";
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internal-codec-playback-dai-link@0 { /* I2S - Internal codec */
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link-name = "WCD";
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cpu { /* PRIMARY */
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sound-dai = <&lpass MI2S_PRIMARY>;
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};
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codec {
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sound-dai = <&lpass_codec 0>, <&wcd_codec 0>;
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};
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};
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internal-codec-capture-dai-link@0 { /* I2S - Internal codec */
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link-name = "WCD-Capture";
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cpu { /* PRIMARY */
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sound-dai = <&lpass MI2S_TERTIARY>;
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};
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codec {
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sound-dai = <&lpass_codec 1>, <&wcd_codec 1>;
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};
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};
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};
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};
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usb2513 {
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@ -278,6 +333,12 @@
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};
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};
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&wcd_codec {
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status = "okay";
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clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
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clock-names = "mclk";
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};
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&smd_rpm_regulators {
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vdd_l1_l2_l3-supply = <&pm8916_s3>;
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vdd_l5-supply = <&pm8916_s3>;
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@ -308,8 +369,8 @@
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};
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l2 {
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regulator-min-microvolt = <375000>;
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regulator-max-microvolt = <1525000>;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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};
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l3 {
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@ -328,8 +389,8 @@
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};
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l6 {
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regulator-min-microvolt = <1750000>;
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regulator-max-microvolt = <3337000>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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l7 {
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@ -388,8 +449,8 @@
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};
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l17 {
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regulator-min-microvolt = <1750000>;
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regulator-max-microvolt = <3337000>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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l18 {
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@ -0,0 +1,15 @@
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#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
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&pm8994_gpios {
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pinctrl-names = "default";
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pinctrl-0 = <&ls_exp_gpio_f>;
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ls_exp_gpio_f: pm8916_mpp4 {
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pinconf {
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pins = "gpio5";
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output-low;
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power-source = <PM8994_GPIO_S4>; // 1.8V
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};
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};
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};
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@ -12,7 +12,9 @@
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*/
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#include "msm8996.dtsi"
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#include "pm8994.dtsi"
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#include "apq8096-db820c-pins.dtsi"
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#include "apq8096-db820c-pmic-pins.dtsi"
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/ {
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aliases {
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@ -77,7 +77,7 @@
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no-map;
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};
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mpss@86800000 {
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mpss_mem: mpss@86800000 {
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reg = <0x0 0x86800000 0x0 0x2b00000>;
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no-map;
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};
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@ -504,6 +504,15 @@
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reg-names = "lpass-lpaif";
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};
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lpass_codec: codec{
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compatible = "qcom,msm8916-wcd-digital-codec";
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reg = <0x0771c000 0x400>;
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clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
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<&gcc GCC_CODEC_DIGCODEC_CLK>;
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clock-names = "ahbix-clk", "mclk";
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#sound-dai-cells = <1>;
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};
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sdhc_1: sdhci@07824000 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0x07824900 0x11c>, <0x07824000 0x800>;
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@ -801,6 +810,49 @@
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clock-names = "iface_clk";
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};
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};
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hexagon@4080000 {
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compatible = "qcom,q6v5-pil";
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reg = <0x04080000 0x100>,
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<0x04020000 0x040>;
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reg-names = "qdsp6", "rmb";
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interrupts-extended = <&intc 0 24 1>,
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<&hexagon_smp2p_in 0 0>,
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<&hexagon_smp2p_in 1 0>,
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<&hexagon_smp2p_in 2 0>,
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<&hexagon_smp2p_in 3 0>;
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interrupt-names = "wdog", "fatal", "ready",
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"handover", "stop-ack";
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clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
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<&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
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<&gcc GCC_BOOT_ROM_AHB_CLK>;
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clock-names = "iface", "bus", "mem";
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qcom,smem-states = <&hexagon_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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resets = <&scm 0>;
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reset-names = "mss_restart";
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mx-supply = <&pm8916_l3>;
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pll-supply = <&pm8916_l7>;
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qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
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status = "disabled";
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mba {
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memory-region = <&mba_mem>;
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};
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mpss {
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memory-region = <&mpss_mem>;
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};
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};
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};
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smd {
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@ -848,6 +900,14 @@
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};
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};
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};
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hexagon {
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interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
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qcom,smd-edge = <0>;
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qcom,ipc = <&apcs 8 12>;
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qcom,remote-pid = <1>;
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};
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};
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hexagon-smp2p {
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@ -0,0 +1,41 @@
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/* Copyright (c) 2015, LGE Inc. All rights reserved.
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "msm8992.dtsi"
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/ {
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model = "LG Nexus 5X";
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compatible = "lg,bullhead", "qcom,msm8992";
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/* required for bootloader to select correct board */
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qcom,board-id = <0xb64 0>;
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qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
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aliases {
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serial0 = &blsp1_uart2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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soc {
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serial@f991e000 {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_uart2_default>;
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pinctrl-1 = <&blsp1_uart2_sleep>;
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};
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};
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};
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
|
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License version 2 and
|
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* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
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|
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&msmgpio {
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blsp1_uart2_default: blsp1_uart2_default {
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pinmux {
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function = "blsp_uart2";
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pins = "gpio4", "gpio5";
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};
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pinconf {
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pins = "gpio4", "gpio5";
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drive-strength = <16>;
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bias-disable;
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};
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};
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blsp1_uart2_sleep: blsp1_uart2_sleep {
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pinmux {
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function = "gpio";
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pins = "gpio4", "gpio5";
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};
|
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pinconf {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. MSM 8992";
|
||||
compatible = "qcom,msm8992";
|
||||
// msm-id needed by bootloader for selecting correct blob
|
||||
qcom,msm-id = <251 0>, <252 0>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
xo_board: xo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
sleep_clk: sleep_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
intc: interrupt-controller@f9000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xf9000000 0x1000>,
|
||||
<0xf9002000 0x1000>;
|
||||
};
|
||||
|
||||
timer@f9020000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0xf9020000 0x1000>;
|
||||
|
||||
frame@f9021000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9021000 0x1000>,
|
||||
<0xf9022000 0x1000>;
|
||||
};
|
||||
|
||||
frame@f9023000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9023000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9024000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9024000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9025000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9025000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9026000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9026000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9027000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9027000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9028000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9028000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
restart@fc4ab000 {
|
||||
compatible = "qcom,pshold";
|
||||
reg = <0xfc4ab000 0x4>;
|
||||
};
|
||||
|
||||
msmgpio: pinctrl@fd510000 {
|
||||
compatible = "qcom,msm8994-pinctrl";
|
||||
reg = <0xfd510000 0x4000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
blsp1_uart2: serial@f991e000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0xf991e000 0x1000>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
|
||||
status = "disabled";
|
||||
clock-names = "core", "iface";
|
||||
clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||||
<&clock_gcc GCC_BLSP1_AHB_CLK>;
|
||||
};
|
||||
|
||||
clock_gcc: clock-controller@fc400000 {
|
||||
compatible = "qcom,gcc-msm8994";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0xfc400000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0 0 0>; // bootloader will update
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
#include "msm8992-pins.dtsi"
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/* Copyright (c) 2015, Huawei Inc. All rights reserved.
|
||||
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "msm8994.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Huawei Nexus 6P";
|
||||
compatible = "huawei,angler", "qcom,msm8994";
|
||||
/* required for bootloader to select correct board */
|
||||
qcom,board-id = <8026 0>;
|
||||
|
||||
aliases {
|
||||
serial0 = &blsp1_uart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
soc {
|
||||
serial@f991e000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&blsp1_uart2_default>;
|
||||
pinctrl-1 = <&blsp1_uart2_sleep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
&msmgpio {
|
||||
blsp1_uart2_default: blsp1_uart2_default {
|
||||
pinmux {
|
||||
function = "blsp_uart2";
|
||||
pins = "gpio4", "gpio5";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
blsp1_uart2_sleep: blsp1_uart2_sleep {
|
||||
pinmux {
|
||||
function = "gpio";
|
||||
pins = "gpio4", "gpio5";
|
||||
};
|
||||
pinconf {
|
||||
pins = "gpio4", "gpio5";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-msm8994.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. MSM 8994";
|
||||
compatible = "qcom,msm8994";
|
||||
// msm-id and pmic-id are required by bootloader for
|
||||
// proper selection of dt blob
|
||||
qcom,msm-id = <207 0x20000>;
|
||||
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen { };
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0x0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 2 0xff08>,
|
||||
<1 3 0xff08>,
|
||||
<1 4 0xff08>,
|
||||
<1 1 0xff08>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
intc: interrupt-controller@f9000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xf9000000 0x1000>,
|
||||
<0xf9002000 0x1000>;
|
||||
};
|
||||
|
||||
timer@f9020000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "arm,armv7-timer-mem";
|
||||
reg = <0xf9020000 0x1000>;
|
||||
|
||||
frame@f9021000 {
|
||||
frame-number = <0>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9021000 0x1000>,
|
||||
<0xf9022000 0x1000>;
|
||||
};
|
||||
|
||||
frame@f9023000 {
|
||||
frame-number = <1>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9023000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9024000 {
|
||||
frame-number = <2>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9024000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9025000 {
|
||||
frame-number = <3>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9025000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9026000 {
|
||||
frame-number = <4>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9026000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9027000 {
|
||||
frame-number = <5>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9027000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
frame@f9028000 {
|
||||
frame-number = <6>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0xf9028000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
restart@fc4ab000 {
|
||||
compatible = "qcom,pshold";
|
||||
reg = <0xfc4ab000 0x4>;
|
||||
};
|
||||
|
||||
msmgpio: pinctrl@fd510000 {
|
||||
compatible = "qcom,msm8994-pinctrl";
|
||||
reg = <0xfd510000 0x4000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
blsp1_uart2: serial@f991e000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0xf991e000 0x1000>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clock-names = "core", "iface";
|
||||
clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
|
||||
<&clock_gcc GCC_BLSP1_AHB_CLK>;
|
||||
};
|
||||
|
||||
tcsr_mutex_regs: syscon@fd484000 {
|
||||
compatible = "syscon";
|
||||
reg = <0xfd484000 0x2000>;
|
||||
};
|
||||
|
||||
clock_gcc: clock-controller@fc400000 {
|
||||
compatible = "qcom,gcc-msm8994";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
reg = <0xfc400000 0x2000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
// We expect the bootloader to fill in the reg
|
||||
reg = <0 0 0 0>;
|
||||
};
|
||||
|
||||
xo_board: xo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
sleep_clk: sleep_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
smem_mem: smem_region@6a00000 {
|
||||
reg = <0x0 0x6a00000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
syscon = <&tcsr_mutex_regs 0 0x80>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
qcom,smem@6a00000 {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_mem>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
#include "msm8994-pins.dtsi"
|
||||
|
|
@ -30,6 +30,42 @@
|
|||
reg = <0 0 0 0>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
mba_region: mba@91500000 {
|
||||
reg = <0x0 0x91500000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
slpi_region: slpi@90b00000 {
|
||||
reg = <0x0 0x90b00000 0x0 0xa00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
venus_region: venus@90400000 {
|
||||
reg = <0x0 0x90400000 0x0 0x700000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
adsp_region: adsp@8ea00000 {
|
||||
reg = <0x0 0x8ea00000 0x0 0x1a00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mpss_region: mpss@88800000 {
|
||||
reg = <0x0 0x88800000 0x0 0x6200000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
smem_mem: smem-mem@86000000 {
|
||||
reg = <0x0 0x86000000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -212,12 +248,29 @@
|
|||
method = "smc";
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
syscon = <&tcsr_mutex_regs 0 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
smem {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_mem>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xffffffff>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
tcsr_mutex_regs: syscon@740000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x740000 0x20000>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@9bc0000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -229,6 +282,11 @@
|
|||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
apcs: syscon@9820000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x9820000 0x1000>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@300000 {
|
||||
compatible = "qcom,gcc-msm8996";
|
||||
#clock-cells = <1>;
|
||||
|
|
@ -458,5 +516,29 @@
|
|||
<825000000>;
|
||||
};
|
||||
};
|
||||
|
||||
adsp-smp2p {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <443>, <429>;
|
||||
|
||||
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
qcom,ipc = <&apcs 16 10>;
|
||||
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <2>;
|
||||
|
||||
adsp_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,state-cells = <1>;
|
||||
};
|
||||
|
||||
adsp_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#include "msm8996-pins.dtsi"
|
||||
|
|
|
|||
|
|
@ -91,9 +91,52 @@
|
|||
};
|
||||
|
||||
pm8916_1: pm8916@1 {
|
||||
compatible = "qcom,spmi-pmic";
|
||||
compatible = "qcom,pm8916", "qcom,spmi-pmic";
|
||||
reg = <0x1 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
wcd_codec: codec@f000 {
|
||||
compatible = "qcom,pm8916-wcd-analog-codec";
|
||||
reg = <0xf000 0x200>;
|
||||
reg-names = "pmic-codec-core";
|
||||
clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
|
||||
clock-names = "mclk";
|
||||
interrupt-parent = <&spmi_bus>;
|
||||
interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf0 0x1 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf0 0x2 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf0 0x3 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf0 0x4 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf0 0x5 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf0 0x6 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf0 0x7 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf1 0x0 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf1 0x1 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf1 0x2 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf1 0x3 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf1 0x4 IRQ_TYPE_NONE>,
|
||||
<0x1 0xf1 0x5 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "cdc_spk_cnp_int",
|
||||
"cdc_spk_clip_int",
|
||||
"cdc_spk_ocp_int",
|
||||
"mbhc_ins_rem_det1",
|
||||
"mbhc_but_rel_det",
|
||||
"mbhc_but_press_det",
|
||||
"mbhc_ins_rem_det",
|
||||
"mbhc_switch_int",
|
||||
"cdc_ear_ocp_int",
|
||||
"cdc_hphr_ocp_int",
|
||||
"cdc_hphl_ocp_det",
|
||||
"cdc_ear_cnp_int",
|
||||
"cdc_hphr_cnp_int",
|
||||
"cdc_hphl_cnp_int";
|
||||
vdd-cdc-io-supply = <&pm8916_l5>;
|
||||
vdd-cdc-tx-rx-cx-supply = <&pm8916_l5>;
|
||||
vdd-micbias-supply = <&pm8916_l13>;
|
||||
#sound-dai-cells = <1>;
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
<0 0xcc 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcd 0 IRQ_TYPE_NONE>,
|
||||
<0 0xce 0 IRQ_TYPE_NONE>,
|
||||
<0 0xcf 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd0 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd1 0 IRQ_TYPE_NONE>,
|
||||
<0 0xd2 0 IRQ_TYPE_NONE>,
|
||||
|
|
|
|||
Loading…
Reference in New Issue