staging: media: tegra-video: add H/V flip controls
Tegra20 can do horizontal and vertical image flip, but Tegra210 cannot (either the hardware, or this driver). In preparation to adding Tegra20 support, add a flag in struct tegra_vi_soc so the generic vi.c code knows whether the flip controls should be added or not. Also provide a generic implementation that simply sets two flags in the channel struct. The Tegra20 implementation will enable flipping at stream start based on those flags. Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
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@ -30,7 +30,7 @@
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#include "vi.h"
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#include "video.h"
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#define MAX_CID_CONTROLS 1
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#define MAX_CID_CONTROLS 3
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/**
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* struct tegra_vi_graph_entity - Entity in the video graph
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@ -912,6 +912,12 @@ static int vi_s_ctrl(struct v4l2_ctrl *ctrl)
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case V4L2_CID_TEGRA_SYNCPT_TIMEOUT_RETRY:
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chan->syncpt_timeout_retry = ctrl->val;
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break;
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case V4L2_CID_HFLIP:
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chan->hflip = ctrl->val;
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break;
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case V4L2_CID_VFLIP:
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chan->vflip = ctrl->val;
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break;
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default:
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return -EINVAL;
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}
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@ -983,6 +989,12 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan)
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v4l2_ctrl_handler_free(&chan->ctrl_handler);
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return ret;
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}
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if (chan->vi->soc->has_h_v_flip) {
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v4l2_ctrl_new_std(&chan->ctrl_handler, &vi_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
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v4l2_ctrl_new_std(&chan->ctrl_handler, &vi_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
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}
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#endif
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/* setup the controls */
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@ -74,6 +74,7 @@ struct tegra_vi_ops {
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* @hw_revision: VI hw_revision
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* @vi_max_channels: supported max streaming channels
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* @vi_max_clk_hz: VI clock max frequency
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* @has_h_v_flip: the chip can do H and V flip, and the driver implements it
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*/
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struct tegra_vi_soc {
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const struct tegra_video_format *video_formats;
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@ -83,6 +84,7 @@ struct tegra_vi_soc {
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u32 hw_revision;
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unsigned int vi_max_channels;
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unsigned int vi_max_clk_hz;
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bool has_h_v_flip:1;
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};
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/**
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@ -172,6 +174,9 @@ struct tegra_vi {
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* @tpg_fmts_bitmap: a bitmap for supported TPG formats
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* @pg_mode: test pattern generator mode (disabled/direct/patch)
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* @notifier: V4L2 asynchronous subdevs notifier
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*
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* @hflip: Horizontal flip is enabled
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* @vflip: Vertical flip is enabled
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*/
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struct tegra_vi_channel {
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struct list_head list;
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@ -222,6 +227,9 @@ struct tegra_vi_channel {
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enum tegra_vi_pg_mode pg_mode;
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struct v4l2_async_notifier notifier;
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bool hflip:1;
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bool vflip:1;
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};
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/**
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