mips: bpf: implement jitting of BPF_ALU | BPF_ARSH | BPF_X
Jitting of BPF_K is supported already, but not BPF_X. This patch complete the support for the latter on both MIPS and microMIPS. Cc: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Acked-by: Paul Burton <paul.burton@mips.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org>
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@ -157,6 +157,7 @@ Ip_u2u1s3(_slti);
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Ip_u2u1s3(_sltiu);
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Ip_u3u1u2(_sltu);
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Ip_u2u1u3(_sra);
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Ip_u3u2u1(_srav);
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Ip_u2u1u3(_srl);
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Ip_u3u2u1(_srlv);
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Ip_u3u1u2(_subu);
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@ -371,6 +371,7 @@ enum mm_32a_minor_op {
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mm_srl32_op = 0x040,
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mm_srlv32_op = 0x050,
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mm_sra_op = 0x080,
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mm_srav_op = 0x090,
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mm_rotr_op = 0x0c0,
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mm_lwxs_op = 0x118,
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mm_addu32_op = 0x150,
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@ -104,6 +104,7 @@ static const struct insn insn_table_MM[insn_invalid] = {
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[insn_sltiu] = {M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM},
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[insn_sltu] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD},
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[insn_sra] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD},
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[insn_srav] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srav_op), RT | RS | RD},
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[insn_srl] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD},
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[insn_srlv] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD},
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[insn_rotr] = {M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD},
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@ -171,6 +171,7 @@ static const struct insn insn_table[insn_invalid] = {
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[insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
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[insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
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[insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE},
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[insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD},
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[insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE},
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[insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD},
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[insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD},
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@ -61,10 +61,10 @@ enum opcode {
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insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
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insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
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insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
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insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl,
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insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
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insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
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insn_xori, insn_yield,
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insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srav,
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insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
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insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh,
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insn_xor, insn_xori, insn_yield,
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insn_invalid /* insn_invalid must be last */
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};
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@ -353,6 +353,7 @@ I_u2u1s3(_slti)
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I_u2u1s3(_sltiu)
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I_u3u1u2(_sltu)
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I_u2u1u3(_sra)
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I_u3u2u1(_srav)
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I_u2u1u3(_srl)
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I_u3u2u1(_srlv)
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I_u2u1u3(_rotr)
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@ -854,6 +854,7 @@ static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
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case BPF_ALU | BPF_MOD | BPF_X: /* ALU_REG */
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case BPF_ALU | BPF_LSH | BPF_X: /* ALU_REG */
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case BPF_ALU | BPF_RSH | BPF_X: /* ALU_REG */
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case BPF_ALU | BPF_ARSH | BPF_X: /* ALU_REG */
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src = ebpf_to_mips_reg(ctx, insn, src_reg_no_fp);
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dst = ebpf_to_mips_reg(ctx, insn, dst_reg);
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if (src < 0 || dst < 0)
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@ -913,6 +914,9 @@ static int build_one_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
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case BPF_RSH:
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emit_instr(ctx, srlv, dst, dst, src);
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break;
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case BPF_ARSH:
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emit_instr(ctx, srav, dst, dst, src);
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break;
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default:
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pr_err("ALU_REG NOT HANDLED\n");
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return -EINVAL;
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