[PATCH] forcedeth: 64-bit DMA support
This is a multi-part message in MIME format. Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Manfred Spraul
Jeff Garzik
parent
c2dba06dae
commit
ee73362cdd
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@ -89,6 +89,7 @@
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* 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
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* 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
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* per-packet flags.
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* 0.39: 18 Jul 2005: Add 64bit descriptor support.
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*
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* Known bugs:
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* We suspect that on some hardware no TX done interrupts are generated.
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@ -100,7 +101,7 @@
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* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
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* superfluous timer interrupts from the nic.
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*/
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#define FORCEDETH_VERSION "0.38"
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#define FORCEDETH_VERSION "0.39"
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#define DRV_NAME "forcedeth"
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#include <linux/module.h>
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@ -138,6 +139,7 @@
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#define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
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#define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
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#define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
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#define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
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enum {
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NvRegIrqStatus = 0x000,
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@ -291,6 +293,18 @@ struct ring_desc {
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u32 FlagLen;
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};
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struct ring_desc_ex {
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u32 PacketBufferHigh;
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u32 PacketBufferLow;
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u32 Reserved;
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u32 FlagLen;
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};
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typedef union _ring_type {
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struct ring_desc* orig;
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struct ring_desc_ex* ex;
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} ring_type;
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#define FLAG_MASK_V1 0xffff0000
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#define FLAG_MASK_V2 0xffffc000
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#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
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@ -405,6 +419,7 @@ struct ring_desc {
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*/
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#define DESC_VER_1 0x0
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#define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
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#define DESC_VER_3 (0x02200|NVREG_TXRXCTL_RXCHECK)
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/* PHY defines */
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#define PHY_OUI_MARVELL 0x5043
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@ -477,7 +492,7 @@ struct fe_priv {
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/* rx specific fields.
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* Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
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*/
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struct ring_desc *rx_ring;
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ring_type rx_ring;
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unsigned int cur_rx, refill_rx;
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struct sk_buff *rx_skbuff[RX_RING];
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dma_addr_t rx_dma[RX_RING];
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@ -494,7 +509,7 @@ struct fe_priv {
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/*
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* tx specific fields.
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*/
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struct ring_desc *tx_ring;
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ring_type tx_ring;
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unsigned int next_tx, nic_tx;
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struct sk_buff *tx_skbuff[TX_RING];
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dma_addr_t tx_dma[TX_RING];
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@ -529,6 +544,11 @@ static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
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& ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
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}
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static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
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{
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return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
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}
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static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
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int delay, int delaymax, const char *msg)
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{
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@ -813,9 +833,16 @@ static int nv_alloc_rx(struct net_device *dev)
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}
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np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
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PCI_DMA_FROMDEVICE);
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np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
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wmb();
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np->rx_ring[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
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wmb();
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np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
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} else {
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np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
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np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
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wmb();
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np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
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}
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dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
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dev->name, refill_rx);
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refill_rx++;
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@ -849,7 +876,10 @@ static void nv_init_rx(struct net_device *dev)
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np->cur_rx = RX_RING;
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np->refill_rx = 0;
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for (i = 0; i < RX_RING; i++)
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np->rx_ring[i].FlagLen = 0;
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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np->rx_ring.orig[i].FlagLen = 0;
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else
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np->rx_ring.ex[i].FlagLen = 0;
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}
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static void nv_init_tx(struct net_device *dev)
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@ -859,7 +889,10 @@ static void nv_init_tx(struct net_device *dev)
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np->next_tx = np->nic_tx = 0;
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for (i = 0; i < TX_RING; i++)
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np->tx_ring[i].FlagLen = 0;
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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np->tx_ring.orig[i].FlagLen = 0;
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else
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np->tx_ring.ex[i].FlagLen = 0;
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}
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static int nv_init_ring(struct net_device *dev)
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@ -874,7 +907,10 @@ static void nv_drain_tx(struct net_device *dev)
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struct fe_priv *np = get_nvpriv(dev);
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int i;
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for (i = 0; i < TX_RING; i++) {
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np->tx_ring[i].FlagLen = 0;
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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np->tx_ring.orig[i].FlagLen = 0;
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else
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np->tx_ring.ex[i].FlagLen = 0;
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if (np->tx_skbuff[i]) {
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pci_unmap_single(np->pci_dev, np->tx_dma[i],
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np->tx_skbuff[i]->len,
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@ -891,7 +927,10 @@ static void nv_drain_rx(struct net_device *dev)
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struct fe_priv *np = get_nvpriv(dev);
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int i;
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for (i = 0; i < RX_RING; i++) {
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np->rx_ring[i].FlagLen = 0;
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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np->rx_ring.orig[i].FlagLen = 0;
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else
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np->rx_ring.ex[i].FlagLen = 0;
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wmb();
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if (np->rx_skbuff[i]) {
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pci_unmap_single(np->pci_dev, np->rx_dma[i],
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@ -922,11 +961,19 @@ static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
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np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
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PCI_DMA_TODEVICE);
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np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
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else {
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np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
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np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
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}
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spin_lock_irq(&np->lock);
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wmb();
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np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
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else
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np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
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dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
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dev->name, np->next_tx);
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{
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@ -964,7 +1011,10 @@ static void nv_tx_done(struct net_device *dev)
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while (np->nic_tx != np->next_tx) {
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i = np->nic_tx % TX_RING;
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Flags = le32_to_cpu(np->tx_ring[i].FlagLen);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
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else
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Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
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dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
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dev->name, np->nic_tx, Flags);
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@ -1035,16 +1085,33 @@ static void nv_tx_timeout(struct net_device *dev)
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}
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printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
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for (i=0;i<TX_RING;i+= 4) {
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printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
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i,
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le32_to_cpu(np->tx_ring[i].PacketBuffer),
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le32_to_cpu(np->tx_ring[i].FlagLen),
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le32_to_cpu(np->tx_ring[i+1].PacketBuffer),
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le32_to_cpu(np->tx_ring[i+1].FlagLen),
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le32_to_cpu(np->tx_ring[i+2].PacketBuffer),
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le32_to_cpu(np->tx_ring[i+2].FlagLen),
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le32_to_cpu(np->tx_ring[i+3].PacketBuffer),
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le32_to_cpu(np->tx_ring[i+3].FlagLen));
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
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i,
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le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
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le32_to_cpu(np->tx_ring.orig[i].FlagLen),
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le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
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le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
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le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
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le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
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le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
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le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
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} else {
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printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
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i,
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le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
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le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
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le32_to_cpu(np->tx_ring.ex[i].FlagLen),
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le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
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le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
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le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
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le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
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le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
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le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
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le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
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le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
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le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
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}
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}
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}
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@ -1061,7 +1128,10 @@ static void nv_tx_timeout(struct net_device *dev)
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printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
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nv_drain_tx(dev);
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np->next_tx = np->nic_tx = 0;
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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else
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
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netif_wake_queue(dev);
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}
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@ -1136,8 +1206,13 @@ static void nv_rx_process(struct net_device *dev)
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break; /* we scanned the whole ring - do not continue */
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i = np->cur_rx % RX_RING;
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Flags = le32_to_cpu(np->rx_ring[i].FlagLen);
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len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
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len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
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} else {
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Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
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len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
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}
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dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
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dev->name, np->cur_rx, Flags);
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@ -1321,7 +1396,10 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
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/* reinit nic view of the rx queue */
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writel(np->rx_buf_sz, base + NvRegOffloadConfig);
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writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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else
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
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writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
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base + NvRegRingSizes);
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pci_push(base);
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@ -1982,7 +2060,10 @@ static int nv_open(struct net_device *dev)
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/* 4) give hw rings */
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writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
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else
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writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
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writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
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base + NvRegRingSizes);
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@ -2173,24 +2254,48 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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}
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/* handle different descriptor versions */
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np->desc_ver = DESC_VER_1;
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np->pkt_limit = NV_PKTLIMIT_1;
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if (id->driver_data & DEV_HAS_LARGEDESC) {
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if (id->driver_data & DEV_HAS_HIGH_DMA) {
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/* packet format 3: supports 40-bit addressing */
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np->desc_ver = DESC_VER_3;
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if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
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printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
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pci_name(pci_dev));
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}
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} else if (id->driver_data & DEV_HAS_LARGEDESC) {
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/* packet format 2: supports jumbo frames */
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np->desc_ver = DESC_VER_2;
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np->pkt_limit = NV_PKTLIMIT_2;
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} else {
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/* original packet format */
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np->desc_ver = DESC_VER_1;
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}
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np->pkt_limit = NV_PKTLIMIT_1;
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if (id->driver_data & DEV_HAS_LARGEDESC)
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np->pkt_limit = NV_PKTLIMIT_2;
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err = -ENOMEM;
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np->base = ioremap(addr, NV_PCI_REGSZ);
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if (!np->base)
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goto out_relreg;
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dev->base_addr = (unsigned long)np->base;
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dev->irq = pci_dev->irq;
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np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
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&np->ring_addr);
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if (!np->rx_ring)
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goto out_unmap;
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np->tx_ring = &np->rx_ring[RX_RING];
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if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
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np->rx_ring.orig = pci_alloc_consistent(pci_dev,
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sizeof(struct ring_desc) * (RX_RING + TX_RING),
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&np->ring_addr);
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if (!np->rx_ring.orig)
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goto out_unmap;
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np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
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} else {
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np->rx_ring.ex = pci_alloc_consistent(pci_dev,
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sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
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&np->ring_addr);
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if (!np->rx_ring.ex)
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goto out_unmap;
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np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
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}
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dev->open = nv_open;
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dev->stop = nv_close;
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|
|
@ -2313,8 +2418,12 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
|
|||
return 0;
|
||||
|
||||
out_freering:
|
||||
pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
|
||||
np->rx_ring, np->ring_addr);
|
||||
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
|
||||
pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
|
||||
np->rx_ring.orig, np->ring_addr);
|
||||
else
|
||||
pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
|
||||
np->rx_ring.ex, np->ring_addr);
|
||||
pci_set_drvdata(pci_dev, NULL);
|
||||
out_unmap:
|
||||
iounmap(get_hwbase(dev));
|
||||
|
|
@ -2343,7 +2452,10 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
|
|||
writel(np->orig_mac[1], base + NvRegMacAddrB);
|
||||
|
||||
/* free all structures */
|
||||
pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
|
||||
if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
|
||||
pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
|
||||
else
|
||||
pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
|
||||
iounmap(get_hwbase(dev));
|
||||
pci_release_regions(pci_dev);
|
||||
pci_disable_device(pci_dev);
|
||||
|
|
@ -2382,35 +2494,35 @@ static struct pci_device_id pci_tbl[] = {
|
|||
},
|
||||
{ /* CK804 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
|
||||
},
|
||||
{ /* CK804 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
|
||||
},
|
||||
{ /* MCP04 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
|
||||
},
|
||||
{ /* MCP04 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
|
||||
},
|
||||
{ /* MCP51 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
|
||||
},
|
||||
{ /* MCP51 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
|
||||
},
|
||||
{ /* MCP55 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
|
||||
},
|
||||
{ /* MCP55 Ethernet Controller */
|
||||
PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
|
||||
.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
|
||||
},
|
||||
{0,},
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue