ixgbe: fix traffic hangs on Tx with ioatdma loaded
When ioatdma was loaded we we were unable to transmit traffic. We weren't using the correct registers in ixgbe_update_tx_dca for 82599 systems. Likewise in ixgbe_configure_tx() we weren't disabling the arbiter before modifying MTQC. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Acked-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -44,6 +44,7 @@
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#include "ixgbe.h"
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#include "ixgbe_common.h"
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#include "ixgbe_dcb_82599.h"
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char ixgbe_driver_name[] = "ixgbe";
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static const char ixgbe_driver_string[] =
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@ -462,19 +463,23 @@ static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
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u32 txctrl;
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int cpu = get_cpu();
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int q = tx_ring - adapter->tx_ring;
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struct ixgbe_hw *hw = &adapter->hw;
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if (tx_ring->cpu != cpu) {
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txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
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if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
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txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
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txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
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txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
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txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
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IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
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} else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
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txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
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txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
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txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
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IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
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IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
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txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
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IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
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}
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txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
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tx_ring->cpu = cpu;
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}
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put_cpu();
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@ -1963,11 +1968,25 @@ static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
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break;
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}
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}
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if (hw->mac.type == ixgbe_mac_82599EB) {
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u32 rttdcs;
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/* disable the arbiter while setting MTQC */
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rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
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rttdcs |= IXGBE_RTTDCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
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/* We enable 8 traffic classes, DCB only */
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if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
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IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
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IXGBE_MTQC_8TC_8TQ));
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else
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IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
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/* re-eable the arbiter */
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rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
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IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
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}
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}
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