soc: samsung: pmu: Remove duplicated define for ARM_L2_OPTION register
The register ARM_L2_OPTION (0x2608 in Exynos4 and Exynos5 PMU) was defined twice. Both names were used in the Exynos542x code. Simplify this. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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@ -388,9 +388,9 @@ static void exynos5420_pm_prepare(void)
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
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pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
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pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
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tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
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tmp = pmu_raw_readl(EXYNOS_L2_OPTION(0));
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tmp &= ~EXYNOS5_USE_RETENTION;
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tmp &= ~EXYNOS_L2_USE_RETENTION;
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pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
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pmu_raw_writel(tmp, EXYNOS_L2_OPTION(0));
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tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
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tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
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tmp |= EXYNOS5420_UFS;
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tmp |= EXYNOS5420_UFS;
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@ -29,7 +29,7 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
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{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
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{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
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{ EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
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{ EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
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{ EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
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{ EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
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{ EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 } },
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{ EXYNOS_L2_OPTION(0), { 0x10, 0x10, 0x0 } },
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{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
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{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
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{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
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{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
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{ EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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{ EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
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@ -230,11 +230,11 @@ static void exynos5420_pmu_init(void)
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pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
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pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
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value = pmu_raw_readl(EXYNOS_L2_OPTION(0));
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value = pmu_raw_readl(EXYNOS_L2_OPTION(0));
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value &= ~EXYNOS5_USE_RETENTION;
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value &= ~EXYNOS_L2_USE_RETENTION;
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pmu_raw_writel(value, EXYNOS_L2_OPTION(0));
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pmu_raw_writel(value, EXYNOS_L2_OPTION(0));
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value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
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value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
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value &= ~EXYNOS5_USE_RETENTION;
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value &= ~EXYNOS_L2_USE_RETENTION;
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pmu_raw_writel(value, EXYNOS_L2_OPTION(1));
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pmu_raw_writel(value, EXYNOS_L2_OPTION(1));
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/*
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/*
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@ -149,8 +149,7 @@
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#define EXYNOS_L2_OPTION(_nr) \
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#define EXYNOS_L2_OPTION(_nr) \
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(EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
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(EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
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#define EXYNOS5_ARM_L2_OPTION 0x2608
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#define EXYNOS_L2_USE_RETENTION BIT(4)
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#define EXYNOS5_USE_RETENTION BIT(4)
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#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
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#define S5P_PAD_RET_MAUDIO_OPTION 0x3028
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#define S5P_PAD_RET_MMC2_OPTION 0x30c8
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#define S5P_PAD_RET_MMC2_OPTION 0x30c8
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