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pinctrl: exynos: Set pin function to EINT in irq_set_type of GPIO EINTa 

Pins used as GPIO interrupts need to be configured as EINTs. This patch
adds the required configuration code to exynos_gpio_irq_set_type,
to set the pin as EINT when its interrupt trigger is configured.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tomasz Figa 2012-09-21 07:33:48 +09:00 committed by Kukjin Kim
parent 011527b45f
commit ee2f573c42
2 changed files with 13 additions and 0 deletions
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12
drivers/pinctrl/pinctrl-exynos.c
View File

@ -76,9 +76,11 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
struct samsung_pinctrl_drv_data *d = irqd->domain->host_data;
struct samsung_pin_ctrl *ctrl = d->ctrl;
struct exynos_geint_data *edata = irq_data_get_irq_handler_data(irqd);
struct samsung_pin_bank *bank = edata->bank;
unsigned int shift = EXYNOS_EINT_CON_LEN * edata->pin;
unsigned int con, trig_type;
unsigned long reg_con = ctrl->geint_con + edata->eint_offset;
unsigned int mask;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@ -110,6 +112,16 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
con &= ~(EXYNOS_EINT_CON_MASK << shift);
con |= trig_type << shift;
writel(con, d->virt_base + reg_con);
reg_con = bank->pctl_offset;
shift = edata->pin * bank->func_width;
mask = (1 << bank->func_width) - 1;
con = readl(d->virt_base + reg_con);
con &= ~(mask << shift);
con |= EXYNOS_EINT_FUNC << shift;
writel(con, d->virt_base + reg_con);
return 0;
}

1
drivers/pinctrl/pinctrl-exynos.h
View File

@ -144,6 +144,7 @@ enum exynos4210_gpio_xc_start {
#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
#define EXYNOS_SVC_OFFSET 0xB08
#define EXYNOS_EINT_FUNC 0xF
/* helpers to access interrupt service register */
#define EXYNOS_SVC_GROUP_SHIFT 3